CAREER: Physical Design Automation for Fast and Reliable 3D Circuits

职业：快速可靠3D电路的物理设计自动化spi: Sung Kyu Lim，佐治亚理工学院3D集成电路是一种新兴技术，可以通过模对模互连垂直堆叠多个芯片。模对模通过间距非常小，并提供了在多个模具上以非常细的粒度排列数字功能块的可能性。这将导致总线长度的减少，从而转化为更少的线延迟和更少的功率。3D集成和封装的进步无疑正在获得动力，并已成为半导体社区的关键兴趣。这些3D集成电路和封装制造技术正迅速被几家领先的公司用于商业应用。尽管3D制造和封装技术发展迅速，但设计自动化社区在开发用于3D集成的计算机辅助设计工具方面进展甚微。本研究的目标是开发3D集成电路的物理设计算法。我们在两个设计抽象级别执行放置和路由：微架构和电路级别。我们的目标是优化性能、功率和尺寸，同时解决几个重要的可靠性问题，如热热点、泄漏功率和电源噪声。该研究的智力价值在于对3D技术如何影响处理器微架构的组织及其电路实现进行了首次详细的分层研究。首先，早在微建筑平面规划阶段的3D感知设计决策对于解决使用3D技术的机遇和挑战至关重要。其次，适当管理热通孔、通硅通孔和去耦电容是缓解3D集成电路中日益恶化的热、漏和电源噪声问题的有效手段。第三，在考虑栅极的统计行为和工艺变化引起的互连延迟的同时，重定时是在性能约束下降低动态和泄漏功率的有力工具。最后，我们正在研究3D时钟网络的一些有趣的拓扑样式，并演示如何在热和电压变化下考虑时钟倾斜变化。这项研究的广泛影响是呼吁来自微架构和EDA/物理设计领域的研究人员之间进行强有力的合作，这将架起学科之间的桥梁，以提供更好的处理器技术。同样，从事研究的学生正在获得多学科和跨领域的经验，从电路设计、物理设计、热建模和噪声建模等低级领域，到高级主题，包括微架构设计和多目标/多约束优化算法。

CAREER: Physical Design Automation for Fast and Reliable 3D CircuitsPI: Sung Kyu Lim, Georgia Institute of TechnologyThe 3D integrated circuit is an emergent technology that vertically stacks multiple die with a die-to-die interconnect. The die-to-die via pitch is very small and provides the possibility of arranging digital functional blocks across multiple die at a very fine level of granularity. This results in a decrease in the overall wire length, which translates into less wire delay and less power. Advances in 3D integration and packaging are undoubtedly gaining momentum and have become of critical interest to the semiconductor community. These 3D integrated circuit and package manufacturing technologies are rapidly being adopted by several leading companies for commercial applications. In spite of the rapid advancement in 3D fabrication and packaging technologies, the design automation community has seen very little progress on the development of computer-aided design tools for 3D integration. The goal of this research is to develop physical design algorithms for 3D integrated circuits. We perform placement and routing at two levels of design abstraction: microarchitecture and circuit level. Our objective is to optimize performance, power, and size while addressing several important reliability issues such as thermal hot-spot, leakage power, and power-supply noise.The intellectual merit of the research is to conduct the first detailed hierarchical study on how 3D technology impacts the organization of processor microarchitectures and their circuit implementation. First, 3D-aware design decisions as early as in the microarchitectural floorplanning stage are crucial in addressing the opportunities and challenges for using 3D technology. Second, a proper management of the thermal-via, through-the-silicon-via, and decoupling capacitor is a highly effective means of alleviating the ever-worsening thermal, leakage, and power-supply noise problems in 3D integrated circuits. Third, retiming is a powerful tool to reduce both dynamic and leakage power under performance constraints while considering the statistical behavior of the gate and interconnect delay caused by process variations. Finally, we are investigating a number of interesting topology styles for the 3D clock network and demonstrate how to consider clock skew variation under thermal and voltage variations. The broader impact of the research is to call for a very strong collaboration between researchers from the microarchitecture and EDA/physical design areas that will bridge the disciplines to deliver better processor technologies. Similarly, students working on the research are gaining multi-disciplinary and cross-cutting experience from low-level areas such as circuit design, physical design, thermal modeling, and noise modeling, to high-level topics, including microarchitecture design and multi-objective/multi-constraint optimization algorithms.