Bringing Low Power Reconfigurable Analog Signal Processing to Embedded Systems

将低功耗可重构模拟信号处理引入嵌入式系统

• 批准号: 0411149
• 负责人: Sung Lim
• 金额: --
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-01 至 2008-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0411149&HistoricalAwards=false
• 关键词: Bringing; Low; Power; Reconfigurable; Analog

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically reduce the power consumption while growing in size, flexibility and usefulness. The goal of this project is to develop the first mapping algorithm for floating-gate-based large-scale FPAAs. The target FPAA device consists of floating-gate transistors, which are standard pFET devices whose gate terminals are not connected to signals except through capacitors. Because the gate terminal is well insulated from external signals, the floating gate can maintain a permanent charge. The computational logic in the FPAA is organized in a compact computational analog block (CAB) that consists of op-amps, transistors, multiplier, programmable capacitors, and filters. CABs are tiled across the chip in a regular mesh-type architecture with busses and local interconnects between them. The major parasitic effects on FPAA chips are due to parasitic resistance and capacitance on FPAA interconnects. Therefore, the primary objective during mapping is to minimize the total number of wireless and switches involved in each interconnect. The mapping process is divided into three: CAP clustering, CAP placement, and FPAA routing. The CAB clustering algorithm tries to group analog components in the given circuit into CAB clusters under the device and wire constraints. During CAP placement, each CAB cluster is assigned to a unique CAB slot in the given FPAA architecture so that the wirelength, congestion, and performance degradation are minimized simultaneously. The FPAA router initially routes each interconnect by the shortest path while ignoring any overuse of routing resources. Then it sequentially performs ripping-up and re-routing every connection to minimize overuse of routing resources in the routing solution. The proposed mapping technology is being transferred to a startup company, and tools and training materials are made widely available through an on-line streaming video course. Graduate students involved are gaining experience in digital/analog signal processing, mixed-signal system design, and physical layout automation algorithms.

现代可重构模拟技术的进步使得现场可编程模拟阵列 (FPAA) 能够大幅降低功耗，同时尺寸、灵活性和实用性不断提高。 该项目的目标是开发第一个用于基于浮栅的大规模 FPAA 的映射算法。 目标 FPAA 器件由浮栅晶体管组成，它们是标准 pFET 器件，其栅极端子除了通过电容器外不连接到信号。 由于栅极端子与外部信号绝缘良好，因此浮动栅极可以保持永久电荷。 FPAA 中的计算逻辑被组织在一个紧凑的计算模拟块 (CAB) 中，该块由运算放大器、晶体管、乘法器、可编程电容器和滤波器组成。 CAB 以规则的网状架构平铺在整个芯片上，它们之间有总线和本地互连。 FPAA 芯片上的主要寄生效应是由于 FPAA 互连上的寄生电阻和电容造成的。 因此，映射期间的主要目标是最小化每个互连中涉及的无线和交换机的总数。 映射过程分为三个：CAP聚类、CAP放置和FPAA路由。 CAB 聚类算法尝试在器件和线路约束下将给定电路中的模拟元件分组为 CAB 簇。 在 CAP 放置期间，每个 CAB 集群都被分配给给定 FPAA 架构中的唯一 CAB 插槽，以便同时最大限度地减少线长、拥塞和性能下降。 FPAA 路由器最初通过最短路径对每个互连进行路由，同时忽略路由资源的任何过度使用。 然后，它按顺序执行每个连接的断开和重新路由，以最大限度地减少路由解决方案中路由资源的过度使用。 拟议的地图技术正在转让给一家初创公司，并且通过在线流媒体视频课程广泛提供工具和培训材料。 参与其中的研究生正在获得数字/模拟信号处理、混合信号系统设计和物理布局自动化算法方面的经验。