SHF:Small:Device/Circuit Co-design of Negative Capacitance Transistors

SHF:Small：负电容晶体管的器件/电路协同设计

• 批准号: 1718671
• 负责人: Sung Lim
• 金额: $ 45万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-09-01 至 2022-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1718671&HistoricalAwards=false
• 关键词: SHF; Small; Device; Circuit; Co

When the supply voltage of a transistor drops, its power consumption reduces significantly but at the cost of delay increase. A scientific breakthrough found in 2008 named negative capacitance states that if a ferroelectric material is used for the gate of a transistor, its delay does not degrade even when the voltage reduces. This remarkable effect has a potential to offer very low power yet high performance electronic switches. Existing studies have demonstrated such benefits at individual transistor-level, but its impact on large-scale circuits and systems has not been well studied. The goal of the proposed research is to quantify these benefits first and then to develop ways to further the benefits. The project, by design, is interdisciplinary in nature and will cover a large range of topics from material science, device engineering to circuit design. The project is expected to provide a unique and interdisciplinary experience for the participating graduate and undergraduate students. The STEM outreach and education programs described will help high school and lower-level college students to seek further studies and careers in semiconductor science and engineering.The team proposes a holistic approach to negative capacitance transistor technology that incorporates experimental research at the most fundamental material-device level, going all the way up to the full chip level circuit simulations. They will develop physics-based compact models for their experimental devices and use these experimentally calibrated models to investigate the performance of negative capacitance transistors corresponding to advance technology nodes such as 10 nm and 7 nm. These models will serve as the intermediary that will translate the results from the basic experiments for chip-level simulations. Large-scale full-chip designs targeting internet-of-things to high-performance applications will be built and optimized to maintain the device superiority all the way up to system and circuit-level. For negative capacitance technology to successfully resolve the power dissipation bottleneck in computing and spur new paradigms in electronics, disjoint research in each individual levels in the hierarchy will not bring about the necessary breakthroughs. The team will develop an approach where all aspects of physics, materials, devices, compact models and circuits are optimized in a self-consistent manner.

当晶体管的电源电压下降时，其功耗显著降低，但代价是延迟增加。2008年发现的一项名为负电容的科学突破指出，如果将铁电材料用于晶体管的栅极，即使电压降低，其延迟也不会降低。这种显著的效果具有提供非常低功率但高性能的电子开关的潜力。现有的研究已经在单个晶体管层面证明了这种好处，但它对大规模电路和系统的影响尚未得到很好的研究。拟议研究的目标是首先量化这些效益，然后制定进一步效益的方法。该项目的设计是跨学科的，将涵盖从材料科学，器件工程到电路设计的广泛主题。该项目预计将提供一个独特的和跨学科的经验，为参与研究生和本科生。STEM推广和教育计划将帮助高中和低年级的大学生在半导体科学和工程领域寻求进一步的学习和职业。该团队提出了一种全面的负电容晶体管技术方法，包括最基本的材料-器件级别的实验研究，一直到完整的芯片级电路模拟。他们将为其实验器件开发基于物理的紧凑模型，并使用这些实验校准的模型来研究与10 nm和7 nm等先进技术节点相对应的负电容晶体管的性能。这些模型将作为中介，将基本实验的结果转化为芯片级仿真。针对物联网到高性能应用的大规模全芯片设计将被构建和优化，以保持器件的优越性，一直到系统和电路级。为了使负电容技术成功地解决计算中的功耗瓶颈并激发电子学的新范式，层次结构中每个单独级别的不相交研究将不会带来必要的突破。该团队将开发一种方法，其中物理，材料，设备，紧凑模型和电路的所有方面都以自洽的方式进行优化。

项目成果

On the Microscopic Origin of Negative Capacitance in Ferroelectric Materials: A Toy Model

• DOI: 10.1109/iedm.2018.8614574
• 发表时间: 2018-12
• 期刊: 2018 IEEE International Electron Devices Meeting (IEDM)
• 作者: A. Khan

Cross-Domain Optimization of Ferroelectric Parameters for Negative Capacitance Transistors—Part I: Constant Supply Voltage

负电容晶体管铁电参数的跨域优化——第一部分：恒定电源电压

• DOI: 10.1109/ted.2019.2955018
• 发表时间: 2020
• 期刊: IEEE Transactions on Electron Devices
• 影响因子: 3.1
• 作者: Pentapati, Sai;Perumal, Rakesh;Khandelwal, Sourabh;Hoffmann, Michael;Lim, Sung Kyu;Khan, Asif I.
• 通讯作者: Khan, Asif I.

Antiferroelectricity in lanthanum doped zirconia without metallic capping layers and post-deposition/-metallization anneals

• DOI: 10.1063/1.5037185
• 发表时间: 2018-05
• 期刊: Applied Physics Letters
• 影响因子: 4
• 作者: Z. Wang;Anthony A. Gaskell;M. Dopita;D. Kriegner;Nujhat Tasneem;Jerry Mack;N. Mukherjee;Z. Karim;A. Khan

Full Chip Power Benefits with Negative Capacitance FETs

负电容 FET 带来全芯片功率优势

• 发表时间: 2017
• 期刊: Proceedings - International Symposium on Low Power Electronics and Design
• 作者: Samal, Sandeep;Khandelwal, Sourabh;Khan, Asif;Salahuddin, Sayeef;Hu, Chenming;Lim, Sung Kyu
• 通讯作者: Lim, Sung Kyu

Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering

• DOI: 10.1109/iedm.2018.8614586
• 发表时间: 2018-12
• 期刊: 2018 IEEE International Electron Devices Meeting (IEDM)
• 作者: Z. Wang;Brian Crafton;Jorge Gomez;R. Xu;Aileen Luo;Z. Krivokapic;L. Martin;S. Datta;A. Raychowdhury;A. Khan