CSR-AES: Parallelizing Irregular Applications for Multicore Processors

计算机行业正在发生根本性的变化。CPU芯片制造商利用先进的半导体技术来增加处理器芯片上的核数，而不是提高时钟频率，从而增加功耗。这就把提高程序性能的负担从芯片制造商转移到了软件开发者身上。许多行业专家认为，多核处理器编程是目前软件行业面临的最重要的挑战。并行架构的编译器技术对于使用诸如树和图之类的链接数据结构的不规则应用程序是无效的。这些数据结构在图形、网格生成和线性系统求解等重要应用领域中无处不在。本课题开发了一种多核处理器并行化和优化不规则程序的新方法。关键的观点是，乐观并行化对于不规则程序至关重要。事务性内存是实现乐观并行化的一种有吸引力的方式；该项目将设计、实现和评估新的事务模型，这些模型利用高级程序抽象的属性，而不是简单地跟踪低级的读写。结果将通过出版物和使软件事务性存储系统可供下载来传播。向主要公司转让技术是传播成果的另一个途径。

NSF Award AbstractThere is a fundamental change ongoing in the computer industry. Instead of increasing clock frequency, which increases power dissipation, CPU chip manufacturers are using advances in semiconductor technology to increase the number of cores on a processor chip. This shifts the burden of improving program performance from chip manufacturers to software developers. Many industry experts believe that programming multicore processors is now the most important challenge facing the software industry.Compiler technology for parallel architectures is not effective for irregular applications that use linked data structures such as trees and graphs. These data structures are ubiquitous in important application areas like graphics, mesh generation and linear system solvers.This project develops a new approach for parallelizing and optimizing irregular programs for multicore processors. The key insight is that optimistic parallelization is essential for irregular programs. Transactional memory is an attractive way to implement optimistic parallelization; this project will design, implement and evaluate new transactional models that exploit properties of high-level program abstractions rather than simply tracking low-level reads and writes.Results will be disseminated through publications and by making the software transactional memory system available for downloading. Technology transfer to leading companies is another avenue for disseminating results.