CSR-AES: Parallelizing Irregular Applications for Multicore Processors

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NSF Award AbstractThere is a fundamental change ongoing in the computer industry. Instead of increasing clock frequency, which increases power dissipation, CPU chip manufacturers are using advances in semiconductor technology to increase the number of cores on a processor chip. This shifts the burden of improving program performance from chip manufacturers to software developers. Many industry experts believe that programming multicore processors is now the most important challenge facing the software industry.Compiler technology for parallel architectures is not effective for irregular applications that use linked data structures such as trees and graphs. These data structures are ubiquitous in important application areas like graphics, mesh generation and linear system solvers.This project develops a new approach for parallelizing and optimizing irregular programs for multicore processors. The key insight is that optimistic parallelization is essential for irregular programs. Transactional memory is an attractive way to implement optimistic parallelization; this project will design, implement and evaluate new transactional models that exploit properties of high-level program abstractions rather than simply tracking low-level reads and writes.Results will be disseminated through publications and by making the software transactional memory system available for downloading. Technology transfer to leading companies is another avenue for disseminating results.