GOALI: A Machine-Learning Approach to Built-In Self-Test of Mixed-Signal/RF Circuits
GOALI:混合信号/射频电路内置自测试的机器学习方法
基本信息
- 批准号:0622081
- 负责人:
- 金额:--
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2006
- 资助国家:美国
- 起止时间:2006-09-01 至 2009-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
ECS-0622081Y. Makris, Yale UniversityWe will develop Built-In Self-Test (BIST) solutions for mixed-signal/RF circuits. BIST is a very important capability of electronic circuits, which allows them to examine their operational health in the field of operation and report potential malfunctions. The current state-of-the-art lacks BIST solutions for mixed-signal/RF circuits, mainly because most known test methods for these circuits rely on a functional test approach, which is impossible to implement on-chip. To mitigate this problem, in this project we will follow an alternative test approach based on machine-learning, wherein a neural classifier, trained through a representative chip population, will examine a set of simple measurements and will decide whether the chip is healthy or not. Efforts will be directed to two main areas, namely the design of on-chip circuitry for generation of test stimuli and acquisition of discriminative measurements and the design of neural classifiers for on-chip machine learning. Two mixed-signal/RF integrated circuits, namely a switched-capacitor filter and a low-noise amplifier will be designed and fabricated through National Semiconductor, the industrial collaborator of this project, in order to demonstrate the feasibility and effectiveness of machine learning-based BIST. The proposed research will be complemented by various educational and outreach activities, including the development of a new graduate-level seminar on Applications of Machine-Learning in Computer Aided Design and Test, participation of undergraduates in research, and promotion of active learning in the design of testable and reliable electronics.Intellectual Merit: This project aims to develop Built-In Self-Test (BIST) solutions for mixed-signal/RF circuits. BIST is a very important capability of electronic circuits, which allows them to examine their operational health in the field of operation and report potential malfunctions. The current state-of-the-art lacks BIST solutions for mixed-signal/RF circuits, mainly because most known test methods for these circuits rely on a functional test approach, which is impossible to implement on-chip. To mitigate this problem, this project follows an alternative test approach based on machine-learning, wherein a neural classifier, trained through a representative chip population, examines a set of simple measurements and decides whether the chip is healthy or not. Efforts will be directed to two main areas, namely the design of on-chip circuitry for generation of test stimuli and acquisition of discriminative measurements and the design of neural classifiers for on-chip machine learning. Two mixed-signal/RF integrated circuits will be designed and fabricated to demonstrate the feasibility and effectiveness of machine-learning-based BIST.Broader Impact: This project will facilitate the realization of testable and reliable electronic circuits and systems, thus extending their deployment in a broad range of applications, enabling reliable computing, and fostering technology trustworthiness. The proposed research is complemented by various educational and outreach activities, including the development of a new graduate-level seminar on Applications of Machine-Learning in Computer Aided Design and Test, participation of undergraduates in research, and promotion of active learning in the design of reliable electronics through involvement with the Yale University solar car racing Team Lux.
ECS-0622081Y。Makris,耶鲁大学我们将为混合信号/RF电路开发内建自测试(BIST)解决方案。BIST是电子电路的一种非常重要的能力,它允许它们在操作领域检查其操作健康状况并报告潜在的故障。目前最先进的技术缺乏用于混合信号/RF电路的BIST解决方案,主要是因为这些电路的大多数已知测试方法依赖于功能测试方法,这是不可能在片上实现的。为了缓解这个问题,在这个项目中,我们将遵循一种基于机器学习的替代测试方法,其中通过代表性芯片群体训练的神经分类器将检查一组简单的测量结果,并决定芯片是否健康。努力将针对两个主要领域,即芯片上的电路的设计,用于生成测试刺激和采集的歧视性测量和设计的神经分类器的芯片上的机器学习。两个混合信号/RF集成电路,即开关电容滤波器和低噪声放大器,将由该项目的工业合作者National Semiconductor设计和制造,以证明基于机器学习的BIST的可行性和有效性。建议的研究将辅以各种教育和外展活动,包括开发一个新的研究生级别研讨会,主题为机器学习在计算机辅助设计和测试中的应用,本科生参与研究,以及促进在可测试和可靠的电子设计方面的主动学习。本项目旨在为混合信号/RF电路开发内建自测试(BIST)解决方案。BIST是电子电路的一种非常重要的能力,它允许它们在操作领域检查其操作健康状况并报告潜在的故障。目前最先进的技术缺乏用于混合信号/RF电路的BIST解决方案,主要是因为这些电路的大多数已知测试方法依赖于功能测试方法,这是不可能在片上实现的。为了缓解这个问题,该项目采用了一种基于机器学习的替代测试方法,其中通过代表性芯片群体训练的神经分类器检查一组简单的测量结果,并决定芯片是否健康。努力将针对两个主要领域,即芯片上的电路的设计,用于生成测试刺激和采集的歧视性测量和设计的神经分类器的芯片上的机器学习。更广泛的影响:该项目将促进可测试和可靠的电子电路和系统的实现,从而扩展其在广泛应用中的部署,实现可靠的计算,并促进技术可信度。拟议的研究是由各种教育和推广活动的补充,包括开发一个新的研究生级别的研讨会机器学习在计算机辅助设计和测试中的应用,本科生参与研究,并通过参与耶鲁大学太阳能汽车赛车队勒克斯促进主动学习可靠的电子产品的设计。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Yiorgos Makris其他文献
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
- DOI:
10.1023/a:1013723905896 - 发表时间:
2002-02-01 - 期刊:
- 影响因子:1.300
- 作者:
Yiorgos Makris;Jamison Collins;Alex Orailoğlu - 通讯作者:
Alex Orailoğlu
RTL Test Justification and Propagation Analysis for Modular Designs
- DOI:
10.1023/a:1008301720070 - 发表时间:
1998-10-01 - 期刊:
- 影响因子:1.300
- 作者:
Yiorgos Makris;Alex Orailogcaron;lu - 通讯作者:
Alex Orailogcaron;lu
An Analog Checker with Input-Relative Tolerance for Duplicate Signals
- DOI:
10.1023/b:jett.0000042512.77744.d5 - 发表时间:
2004-10-01 - 期刊:
- 影响因子:1.300
- 作者:
Haralampos-G. D. Stratigopoulos;Yiorgos Makris - 通讯作者:
Yiorgos Makris
Yiorgos Makris的其他文献
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{{ truncateString('Yiorgos Makris', 18)}}的其他基金
CISE-ANR: SHF: Small: CHAMELEON: CompreHending And Mitigating Error in AnaLog ImplEmentations of On-Die Neural Networks
CISE-ANR:SHF:小:CHAMELEON:理解并减轻片上神经网络模拟实现中的错误
- 批准号:
2214934 - 财政年份:2022
- 资助金额:
-- - 项目类别:
Standard Grant
SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Integrated Circuit Design
SaTC:TTP:中:通过混合 ASIC/TRAP 集成电路设计保护硬件知识产权
- 批准号:
2155208 - 财政年份:2022
- 资助金额:
-- - 项目类别:
Standard Grant
Phase I IUCRC University of Texas at Dallas: Center for Hardware and Embedded System Security and Trust (CHEST)
第一阶段 IUCRC 德克萨斯大学达拉斯分校:硬件和嵌入式系统安全与信任中心 (CHEST)
- 批准号:
1916750 - 财政年份:2019
- 资助金额:
-- - 项目类别:
Continuing Grant
Planning IUCRC University of Texas at Dallas: Center for Hardware and Embedded System Security and Trust (CHEST)
规划 IUCRC 德克萨斯大学达拉斯分校:硬件和嵌入式系统安全与信任中心 (CHEST)
- 批准号:
1747773 - 财政年份:2018
- 资助金额:
-- - 项目类别:
Standard Grant
Student Travel Support for 2017 IEEE VLSI Test Symposium
2017 年 IEEE VLSI 测试研讨会学生旅行支持
- 批准号:
1735673 - 财政年份:2017
- 资助金额:
-- - 项目类别:
Standard Grant
Student Travel Support for 2016 IEEE VLSI Test Symposium
2016 年 IEEE VLSI 测试研讨会学生旅行支持
- 批准号:
1639728 - 财政年份:2016
- 资助金额:
-- - 项目类别:
Standard Grant
TWC: Medium: Hardware Trojans in Wireless Networks - Risks and Remedies
TWC:中:无线网络中的硬件木马 - 风险和补救措施
- 批准号:
1514050 - 财政年份:2015
- 资助金额:
-- - 项目类别:
Standard Grant
SHF: Small: On-Die Learning: A Pathway to Post-Deployment Robustness and Trustworthiness of Analog/RF ICs
SHF:小型:片上学习:实现模拟/射频 IC 部署后稳健性和可信度的途径
- 批准号:
1527460 - 财政年份:2015
- 资助金额:
-- - 项目类别:
Standard Grant
TWC: Small: Collaborative: Toward Trusted Third-Party Microprocessor Cores: A Proof Carrying Code Approach
TWC:小型:协作:走向可信的第三方微处理器核心:携带代码的证明方法
- 批准号:
1318860 - 财政年份:2013
- 资助金额:
-- - 项目类别:
Standard Grant
Cross-Layer Intelligent System-Based Adaptive Power Conditioning for Robust and Reliable Mixed-Signal Multi-Core SoCs
基于跨层智能系统的自适应功率调节,用于稳健可靠的混合信号多核 SoC
- 批准号:
1255754 - 财政年份:2013
- 资助金额:
-- - 项目类别:
Continuing Grant
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