SBIR Phase I: Novel Slurry for Direct Shallow Trench Isolation (STI) Planarization Process for Sub-50 nm Devices

SBIR 第一阶段：用于 50 nm 以下器件直接浅沟槽隔离 (STI) 平坦化工艺的新型浆料

• 批准号: 0637261
• 负责人: Deepika Singh
• 金额: --
• 依托单位: SINMAT, INC.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-01-01 至 2007-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0637261&HistoricalAwards=false
• 关键词: SBIR; Phase; Novel; Slurry; Direct

This Small Business Innovation Research (SBIR) project proposes to develop a novel single step shallow trench isolation (STI) planarization. An ideal STI Chemical Mechanical Planarization (CMP) process is expected to be a single step process, which directly and rapidly removes the overburden dielectric layer with minimum topography formation or defect generation. However, the present state of the art processes areplagued with several challenges including (a) poor planarization, (b) small processing window, and (c) high defectivity. We propose to develop a novel high planarity and high selectivity (HP-HS) direct STI CMP process based on combination of coated silica particles and chemical additives. The unique feature of this process is the use of surfactant additives in combination with coated particles to obtain non-linear pressuredependent polishing characteristics, which results in high planarity polishing of the silica surface. The successful implementation of the single step STI CMP process is expected to meet or exceed the technical performance levels of the 45 nm manufacturing node while decreasing chip manufacturing costs by up to $800 million. The reduction in costs is largely due to the simplification of the manufacturing process, higher throughput and increased yield.

这个小型企业创新研究（SBIR）项目提出开发一种新颖的单步浅沟槽隔离（STI）平面化。理想的STI化学机械平坦化（CMP）工艺预期为单步工艺，其直接且快速地移除过覆电介质层，同时最小化形貌形成或缺陷产生。然而，现有技术的工艺受到几个挑战的困扰，包括（a）差的平面化，（B）小的处理窗口，和（c）高缺陷率。我们提出了一种新的高平面性和高选择性（HP-HS）直接STI CMP工艺的基础上结合涂层二氧化硅颗粒和化学添加剂。该工艺的独特之处在于使用表面活性剂添加剂与涂层颗粒相结合，以获得非线性的压力依赖性抛光特性，从而实现二氧化硅表面的高平面度抛光。单步STI CMP工艺的成功实施有望达到或超过45纳米制造节点的技术性能水平，同时将芯片制造成本降低高达8亿美元。成本的降低主要是由于制造工艺的简化、更高的产量和更高的产量。