Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic

项目ID：0702831和0702628 PI(S)：Sarma Vrudhula and Spyros Tragoudas标题：使用阈值逻辑对纳米CMOS及以上进行合成、验证和测试机构：亚利桑那州立大学及简介到2020年，当硅的厚度将小于几个原子的堆叠时，半导体行业协会的路线图预测，进一步扩大CMOS电路的规模将是不可持续的，并预计从CMOS过渡到一种或多种目前新兴的纳米技术，如共振隧道二极管(RTD)、碳纳米管场效应晶体管(CNFET)和碳纳米线。未来还有单电子晶体管(SET)和量子细胞自动机(QCA)等设备。这些后CMOS纳米技术的一个重要而独特的特征是，它们使高效和自然地实现阈值逻辑(TL)成为可能。虽然时序逻辑的概念从20世纪60年代就已为人所知，但在大型时序逻辑网络的综合和优化方面还没有全面的工作，就像我们在过去30年中看到的传统CMOS逻辑门网络的综合和优化一样。这是一项建议，旨在开发一种全面的设计方法，包括TL网络的综合、优化、验证和测试。我们建议研究从独立于技术的、电路的功能描述开始的综合算法。TL网络的优化带来了独特的问题。无论底层技术如何，TL门都是通过将输入的加权和与给定阈值进行比较来实现的。这可以是电压或电流的比较。由于工艺变化会改变这种比较的结果，它们不仅会影响性能和功率，还会改变门实现的功能。我们将其称为功能收益率(FY)。我们将开发新的算法，在器件长度、宽度、阈值电压、氧化层厚度等工艺变量空间内联合最大化TL网络的FY、功耗和性能。还将开发使用新的参数故障模型测试所制造电路的功能正确性和延迟的方法。验证TL网络与给定功能规范的等价性尚未解决。当设计参数被表示为工艺变化模型的统计量时，这对于验证合成过程的结果以及确定功能产量是必不可少的。这项工作的预期结果包括：用于TL门的新的CMOS和后CMOS电路架构；用于自动综合、执行功能验证和生成TL电路的测试图形的算法和工具；计算TL网络的参数成品率的方法，将TL网络参数建模为相关的随机变量；在工艺变量空间执行TL网络的功能成品率、功耗和性能的联合优化的方法。

Project Id: 0702831 and 0702628 PI(s): Sarma Vrudhula and Spyros TragoudasTitle: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold LogicInstitutions: Arizona State University & ABSTRACTBy 2020, when thickness of Silicon will be less than a stack of a few atoms, the Semiconductor Industry Association roadmap predicts that further scaling CMOS circuits will not be sustainable, and expects a transition from CMOS to one or more of the presently nascent nano technologies such as resonant tunneling diodes (RTD), carbon nanotube FETs (CNFET) and carbon nanowires. Further in the future are devices such as single electron transistors (SET), and quantum cellular automata (QCA). An important and distinctive characteristic of these post-CMOS nano technologies is that they make it possible to efficiently and naturally implement threshold logic (TL). While TL concepts have been known since the 1960s, there has been no comprehensive work on synthesis and optimization of large TL networks similar to what we have witnessed over the past 30 years for traditional CMOS logic gate networks. This is a proposal to develop a comprehensive design methodology encompassing synthesis, optimization, verification, and testing of TL networks. We propose to investigate synthesis algorithms that start with a technology independent, functional description of the circuit. Optimization of TL networks poses unique problems. Regardless of the underlying technology, TL gates are realized by comparing the weighted sum of the inputs with a given threshold. This can be a comparison of voltages or currents. Since process variations can change the outcome of such a comparison, they not only effect the performance and power but can also change the function realized by the gate. We refer to this as the functional yield (FY). We will develop new algorithms that jointly maximize the FY, power consumption, and performance of a TL network over the space of process variables, e.g. device lengths, widths, threshold voltages, oxide thicknesses, etc. Methods for testing the manufactured circuit for functional correctness and delay using new parametric fault models will also be developed. Verifying the equivalence of a TL network to a given a functional specification has not yet been addressed. This is essential for verifying the result of the synthesis procedure as well as in determining the functional yield when the design parameters are represented as statistical quantities as models of process variations. Expected outcomes of this effort include: new CMOS and post-CMOS circuit architectures for TL gates; algorithms and tools to automatically synthesize, perform functional verification and generate test patterns for TL circuits; methods to compute the parametric yield of TL networks, modeling TL network parameters as correlated random variables; methods to perform joint optimization of functional yield, power consumption and performance of TL networks over the space of process variables.