Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic

项目ID：0702831和0702628 PI（s）：Sarma Vrudhula和Spyros Tragoudas标题：使用阈值逻辑的纳米CMOS及以上的合成、验证和测试机构：亚利桑那州立大学摘要到2020年，当硅的厚度将小于几个原子的堆叠时，半导体工业协会路线图预测进一步缩放CMOS电路将是不可持续的&，并期望从CMOS过渡到一种或多种目前新生的纳米技术，如共振隧穿二极管（RTD）、碳纳米管FET（CNFET）和碳纳米线。 未来还有诸如单电子晶体管（SET）和量子细胞自动机（QCA）之类的器件。这些后CMOS纳米技术的一个重要而独特的特征是，它们可以有效而自然地实现阈值逻辑（TL）。 虽然TL概念自20世纪60年代以来就已为人所知，但在大型TL网络的综合和优化方面，还没有全面的工作，类似于我们在过去30年中所目睹的传统CMOS逻辑门网络。这是一个建议，制定一个全面的设计方法，包括综合，优化，验证和测试的TL网络。我们建议调查合成算法，开始与技术无关，功能描述的电路。TL网络的优化提出了独特的问题。无论底层技术如何，TL门都是通过将输入的加权和与给定阈值进行比较来实现的。这可以是电压或电流的比较。由于工艺变化可以改变这种比较的结果，因此它们不仅影响性能和功率，而且还可以改变由门实现的功能。我们称之为功能产量（FY）。 我们将开发新的算法，共同最大限度地提高FY，功耗和TL网络的性能在工艺变量的空间，例如设备的长度，宽度，阈值电压，氧化层厚度等方法测试制造电路的功能正确性和延迟使用新的参数故障模型也将开发。 然而，TL网络与给定功能规范的等价性尚未得到解决。这对于验证合成过程的结果以及当设计参数被表示为作为过程变化的模型的统计量时确定功能产量是必不可少的。这项工作的预期成果包括：新的CMOS和后CMOS电路结构的TL门;算法和工具，自动合成，执行功能验证和生成测试模式的TL电路;方法来计算参数产量的TL网络，建模TL网络参数作为相关的随机变量;在过程变量空间上对TL网络的功能成品率、功耗和性能进行联合优化的方法。

Project Id: 0702831 and 0702628 PI(s): Sarma Vrudhula and Spyros TragoudasTitle: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold LogicInstitutions: Arizona State University & ABSTRACTBy 2020, when thickness of Silicon will be less than a stack of a few atoms, the Semiconductor Industry Association roadmap predicts that further scaling CMOS circuits will not be sustainable, and expects a transition from CMOS to one or more of the presently nascent nano technologies such as resonant tunneling diodes (RTD), carbon nanotube FETs (CNFET) and carbon nanowires. Further in the future are devices such as single electron transistors (SET), and quantum cellular automata (QCA). An important and distinctive characteristic of these post-CMOS nano technologies is that they make it possible to efficiently and naturally implement threshold logic (TL). While TL concepts have been known since the 1960s, there has been no comprehensive work on synthesis and optimization of large TL networks similar to what we have witnessed over the past 30 years for traditional CMOS logic gate networks. This is a proposal to develop a comprehensive design methodology encompassing synthesis, optimization, verification, and testing of TL networks. We propose to investigate synthesis algorithms that start with a technology independent, functional description of the circuit. Optimization of TL networks poses unique problems. Regardless of the underlying technology, TL gates are realized by comparing the weighted sum of the inputs with a given threshold. This can be a comparison of voltages or currents. Since process variations can change the outcome of such a comparison, they not only effect the performance and power but can also change the function realized by the gate. We refer to this as the functional yield (FY). We will develop new algorithms that jointly maximize the FY, power consumption, and performance of a TL network over the space of process variables, e.g. device lengths, widths, threshold voltages, oxide thicknesses, etc. Methods for testing the manufactured circuit for functional correctness and delay using new parametric fault models will also be developed. Verifying the equivalence of a TL network to a given a functional specification has not yet been addressed. This is essential for verifying the result of the synthesis procedure as well as in determining the functional yield when the design parameters are represented as statistical quantities as models of process variations. Expected outcomes of this effort include: new CMOS and post-CMOS circuit architectures for TL gates; algorithms and tools to automatically synthesize, perform functional verification and generate test patterns for TL circuits; methods to compute the parametric yield of TL networks, modeling TL network parameters as correlated random variables; methods to perform joint optimization of functional yield, power consumption and performance of TL networks over the space of process variables.