I/UCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations

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A significant challenge for embedded systems is developing the high-performance, reliable, low cost, and low-power integrated circuits. This project addresses this challenge by developing accurate testability and timing analysis techniques for integrated circuits. The main objective of this effort is to address timing-related reliability, testing and design challenges faced by the semiconductor industry due to significant increase in process variations. The project will develop new methods for modeling the process variability that benefit from advanced data structures and novel algorithms. A new direction in determining gate delay models in the presence of process variations is investigated. The goal is to reduce modeling errors and is expected to identify critical path delay faults that current methods skip. Moreover, it is expected to result in more accurate estimates for the delay of the circuit.The proposed research activities will help semiconductor companies in developing reliable and faster integrated circuits and microprocessors. This will have impact on the society since cell-phones, cars, airplanes, unmanned vehicles, and biomedical devices are a major factor in the quality of human life. The fundamental modeling of process variations will be developed with the center member companies, ensuring rapid technology transfer and uptake of new methods. The work is supported by the Industry Advisory Board as well as individual industry members of the center and has the potential to extend the center research portfolio while potentially attracting new members. The proposed research will be used as a vehicle to help students develop interests and abilities to conduct research in the VLSI design and test automation area, and undergraduates will be inspired for graduate studies.