Delay Test and Diagnosis Considering DSM and Power

考虑DSM和功率的延迟测试和诊断

• 批准号: 0702669
• 负责人: Duncan Walker
• 金额: $ 15万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-07-15 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702669&HistoricalAwards=false
• 关键词: Delay; Test; Diagnosis; Considering; DSM

Proposal ID: 0702669 PI name: Walker Duncan, MPI Institution: Texas A & M UniversityTitle: Delay Test and Diagnosis Considering DSM and PowerABSTRACTThe goal of this research is to develop semiconductor manufacturing tests that verify the clock frequency of integrated circuits with high confidence but low cost. This is known as "delay test". Delay test is increasingly difficult due to increasing variability in new semiconductor manufacturing processes, and increasing power and wiring densities on the chip.Traditional delay test techniques are becoming too expensive or too inaccurate for their continued use. If a chip is slow, the second goal of this research is to figure out why, so that either the design or the manufacturing process can be fixed, in order to ship chips at the desired clock frequency. This is critical to earning a return on multi-billion dollar factory and design investments. The intellectual merit of the research is that it has the potential to significantly improve chip quality or reduce manufacturing costs. The broader impact is the education of undergraduate and graduate students, and the development of new course materials and software for wider distribution.

提案ID: 0702669 PI名称：Walker Duncan， MPI机构：Texas A & M university标题：考虑DSM和powerabstract的延迟测试和诊断本研究的目标是开发半导体制造测试，以高可信度但低成本地验证集成电路的时钟频率。这就是所谓的“延迟测试”。由于新的半导体制造工艺的可变性增加，以及芯片上功率和布线密度的增加，延迟测试变得越来越困难。传统的延迟测试技术正变得过于昂贵或过于不准确，无法继续使用。如果一个芯片很慢，本研究的第二个目标是找出原因，以便设计或制造过程可以固定，以便以所需的时钟频率发货芯片。这对于获得数十亿美元的工厂和设计投资回报至关重要。这项研究的智力价值在于，它有可能显著提高芯片质量或降低制造成本。更广泛的影响是对本科生和研究生的教育，以及开发新的课程材料和软件以供更广泛的分发。