Built-In IDDQ Sensors for Deep-Submicron Circuits

这项提案是关于开发使用超深亚微米技术构建的VLSI芯片制造测试的新方法。现有的测试方法不能放大，因为将存在增加的背景电流。该方法是通过使用磁场测量技术来探索静态电流(IDDQ)信号方法，并开发和应用内置电流传感器(BIC)来提供区分故障和无故障IDDQ级别的能力。这个问题是由每一代技术产生的亚阈值泄漏电流增加引起的。BICS的设计目标包括微安分辨率、1%的面积开销和1ms的测量时间。此外，该项目正在开发设计方法，将BICS自动放置到网状供应网络中，以实现最大覆盖和最高分辨率。研究问题包括：在BICS校准过程中需要切断电源；考虑到由于工艺、环境和电路状态变化而导致的无故障IDDQ电平的巨大变化。正在探索通过扩展当前的Siganture方法来改进限制设置的方法，方法是使用对正常IDDQ水平的基于模型的估计(来自简单的电学测试)，并利用BICS测量的空间相关性。演示这些想法的算法和软件正在开发中。

This proposal is on developing new methodologies for VLSI chip manufacturing test built using very deep submicron technologies. Existing test methods do not scale up because of increased background currents that will exist. The approach is to explore the quiescent current (IDDQ) signature approach by using magnetic filed measuring techniques, and to develop and apply built-in current sensors (BICS) to provide the ability to distinguish between faulty and fault-free IDDQ levels. This problem is caused by the increase in subthreshold leakage currents with each technology generation. The BICS design goals include microampere resolution, 1% area overhead, and 1 ms measurement time. Further, the project is developing design methods to automatically place BICSs into a mesh-type supply network to achieve maximum coverage and resolution. Research problems include: the need to shut off the power supply during BICS calibration; an accounting for large variations in fault-free IDDQ levels caused by process, environment and circuit state variations. Methods to improve limit setting by extending the current siganture methodology are being explored by using model-based estimates of normal IDDQ levels (derived from simple electrical tests), and by exploiting the spatial correlation of BICS measurements. Algorithms and software demonstrating these ideas are being developed.