Built-In IDDQ Sensors for Deep-Submicron Circuits

这项建议是关于发展新的方法，超大规模集成电路芯片制造测试建立使用非常深的亚微米技术。 现有的测试方法没有按比例放大，因为将存在增加的背景电流。 该方法是探索静态电流（IDDQ）签名的方法，通过使用磁场测量技术，并开发和应用内置电流传感器（BICS），以提供区分故障和无故障IDDQ水平的能力。 这个问题是由每一代技术的亚阈值漏电流增加引起的。 BICS的设计目标包括微安分辨率、1%面积开销和1 ms测量时间。 此外，该项目正在开发设计方法，将BICS自动放入网状供电网络，以实现最大的覆盖范围和分辨率。 研究问题包括：在BICS校准期间需要关闭电源;考虑由工艺、环境和电路状态变化引起的无故障IDDQ电平的大幅变化。 正在探索通过扩展当前的信号方法来提高限值设置的方法，方法是使用基于模型的正常IDDQ水平估计（来自简单的电气测试），并利用BICS测量的空间相关性。 正在开发算法和软件来证明这些想法。

This proposal is on developing new methodologies for VLSI chip manufacturing test built using very deep submicron technologies. Existing test methods do not scale up because of increased background currents that will exist. The approach is to explore the quiescent current (IDDQ) signature approach by using magnetic filed measuring techniques, and to develop and apply built-in current sensors (BICS) to provide the ability to distinguish between faulty and fault-free IDDQ levels. This problem is caused by the increase in subthreshold leakage currents with each technology generation. The BICS design goals include microampere resolution, 1% area overhead, and 1 ms measurement time. Further, the project is developing design methods to automatically place BICSs into a mesh-type supply network to achieve maximum coverage and resolution. Research problems include: the need to shut off the power supply during BICS calibration; an accounting for large variations in fault-free IDDQ levels caused by process, environment and circuit state variations. Methods to improve limit setting by extending the current siganture methodology are being explored by using model-based estimates of normal IDDQ levels (derived from simple electrical tests), and by exploiting the spatial correlation of BICS measurements. Algorithms and software demonstrating these ideas are being developed.