Built-In IDDQ Sensors for Deep-Submicron Circuits

适用于深亚微米电路的内置 IDDQ 传感器

• 批准号: 9971192
• 负责人: Duncan Walker
• 金额: $ 19.33万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-09-01 至 2002-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9971192&HistoricalAwards=false
• 关键词: Built; IDDQ; Sensors; Deep; Submicron

This proposal is on developing new methodologies for VLSI chip manufacturing test built using very deep submicron technologies. Existing test methods do not scale up because of increased background currents that will exist. The approach is to explore the quiescent current (IDDQ) signature approach by using magnetic filed measuring techniques, and to develop and apply built-in current sensors (BICS) to provide the ability to distinguish between faulty and fault-free IDDQ levels. This problem is caused by the increase in subthreshold leakage currents with each technology generation. The BICS design goals include microampere resolution, 1% area overhead, and 1 ms measurement time. Further, the project is developing design methods to automatically place BICSs into a mesh-type supply network to achieve maximum coverage and resolution. Research problems include: the need to shut off the power supply during BICS calibration; an accounting for large variations in fault-free IDDQ levels caused by process, environment and circuit state variations. Methods to improve limit setting by extending the current siganture methodology are being explored by using model-based estimates of normal IDDQ levels (derived from simple electrical tests), and by exploiting the spatial correlation of BICS measurements. Algorithms and software demonstrating these ideas are being developed.

该提案旨在开发使用非常深的亚微米技术构建的 VLSI 芯片制造测试的新方法。 由于存在增加的背景电流，现有的测试方法无法扩大规模。 该方法是利用磁场测量技术探索静态电流 (IDDQ) 特征方法，并开发和应用内置电流传感器 (BICS)，以提供区分有故障和无故障 IDDQ 水平的能力。 这个问题是由于每一代技术中亚阈值漏电流的增加引起的。 BICS 设计目标包括微安分辨率、1% 面积开销和 1 毫秒测量时间。 此外，该项目正在开发设计方法，自动将 BICS 放入网状供应网络中，以实现最大的覆盖范围和分辨率。 研究问题包括：BICS校准时需要关闭电源；考虑到由工艺、环境和电路状态变化引起的无故障 IDDQ 水平的巨大变化。 通过使用基于模型的正常 IDDQ 水平估计（源自简单的电气测试）以及利用 BICS 测量的空间相关性，正在探索通过扩展当前签名方法来改进限制设置的方法。 展示这些想法的算法和软件正在开发中。