Optimizing Memory for Advanced Driver Assistance Systems and Autonomous Driving

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Heterogeneous multi-core architectures enhanced by custom accelerator cores are today widely used in many embedded applications. These types of compute platforms that were originally developed for consumer applications are now entering safety critical applications, especially in the automotive domain where autonomous driving is currently disrupting the conventional automotive electronics development. The immense computing power of such architectures brings further large challenges. The increasing gap between speed of the heterogeneous multi-core architectures and accesses to the main memories poses a severe limit. The dominant type of main memories are Dynamic Random Access Memories (DRAMs) that offer the best trade-off between storage density and access times. Algorithms for Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) in automotive require low latency and huge external memory bandwidth. Thus, the memory bandwidth becomes one of the big bottlenecks. DRAMs are commodity devices optimized for minimum cost per storage bit. Hence, the DRAM package has to be cheap that limits the available package pins. Furthermore, DRAMs have a complex internal architecture with advanced internal prefetching to bridge the gap between external available memory bandwidth and internal latency. DRAM technologies exhibit a large parameter variation (speed sorting) and the storage cells have to be refreshed, which are very sensitive to temperature. These features make it very challenging to use DRAMs in safety critical applications. In recent years many new DRAM memory devices have been presented (e.g. DDR4, LPDDR4, GDDR6, Wide I/O, HMB2). It is not yet clear how these memory modules have to be used and how they will perform in the automotive context with respect to bandwidth, latency, power, temperature, reliability, safety and security. The scientific DRAM research so far mainly focused on mobile devices and data centers. These applications have totally different profiles compared to the safety critical automotive domain. Thus, there is a high need to close this research gap by transferring basic research to industry, taking the automotive application requirements into account. To the best of our knowledge, there are no investigations or publications that optimize the DRAM memory subsystem with respect to future automotive applications. Therefore, in this trilateral transfer project, the results gained from the basic research at TU Kaiserslautern about DRAM modelling, optimization, controllers etc. will be further developed towards applicability for automotive industry. The Fraunhofer IESE will support and coordinate this transfer with their strong background in safety for automotive and embedded systems. The application partner Bosch, one of the major automotive suppliers, will provide detailed application know-how, requirements and concrete research challenges from an industry perspective.