CAREER: Adaptive and Built-in Defect and Fault Tolerance for Crossbar Nano-architectures

CCF-0746836标题：Career：Crosbar Nano-Architecture的自适应和内置缺陷与容错PI名称：Tahoori，Mehdi B.Inst：东北大学摘要：芯片制造技术的进步推动了集成到我们日常生活中的电子系统的惊人增长。然而，这一趋势正面临严峻的挑战，这使得新兴的纳米技术成为未来芯片制造的必然。纳米技术面临的主要挑战是可靠性。与当今芯片中使用的传统器件相比，纳米器件在制造和使用寿命方面都更有可能出现故障。缺陷数量的增加对制造产量产生不利影响，对纳米电子行业造成严重的负面经济影响。该项目侧重于一套完全集成的教育和研究活动，以在存在高缺陷密度的情况下提供缺陷和容错能力。为了容忍高缺陷率，在纳米技术的设计方法中集成了提高制造成品率的缺陷容限(针对制造缺陷)和容错以确保寿命可靠性(针对正常操作中的错误)。目标平台是使用碳纳米管构建的可编程交叉杆纳米体系结构。开发了与传统方法根本不同的自适应和内置缺陷和容错设计流程，其中的目标是以极低的成本确保电路的高制造成品率和运行时可靠性。电路中内置了缺陷和容错功能，最大限度地减少了与昂贵且耗时的片外设备的通信。此外，建议的内置缺陷和容错将自动适应制造和运行时缺陷的级别，使其在广泛的制造工艺、操作环境和应用中处于最佳状态。

CCF - 0746836 Title: CAREER: Adaptive and Built-in Defect and Fault Tolerance for Crossbar Nano-architecturesPI name:Tahoori, Mehdi B.Inst: Northeastern UniversityABSTRACT:Improvements in chip manufacturing technology have propelled an astonishing growth of electronic systems which are integrated into our daily lives. However, this trend is facing serious challenges, making emerging nanotechnologies inevitable for future chip manufacturing. The major challenge for nanotechnologies is reliability. Nanoscale devices are more likely to fail, both at the manufacturing and during the operating lifetime, compared to traditional devices used in today's chips. Elevated number of defects adversely affects the manufacturing yield, causing a severe negative economic impact on the nanoelectronic industry. This project focuses on a set of fully integrated educational and research activities to provide defect and fault tolerance in the presence of high defect densities. To tolerate high defect rates, defect tolerance to improve the manufacturing yield (for fabrication defects) and fault tolerance to ensure the lifetime reliability (for errors during normal operation) are integrated in the design methodologies for nanotechnologies. The target platform is the programmable crossbar nano-architecture built using carbon nanotubes. Adaptive and built-in defect and fault tolerant design flows, fundamentally different from conventional approaches, are developed in which the objective is to ensure high manufacturing yield and runtime reliability of the circuit at extremely low costs. Defect and fault tolerance are built into the circuit, minimizing the communication with expensive and time-consuming off-chip equipments. Moreover, the proposed built-in defect and fault tolerance will automatically adapt to the level of manufacturing and runtime defects, making them optimal for a wide range of fabrication processes, operation environments, and applications.