CAREER: Adaptive and Built-in Defect and Fault Tolerance for Crossbar Nano-architectures

CCF - 0746836标题：职业：纵横纳米架构的自适应和内置缺陷和容错PI姓名：Tahoori，Mehdi B.研究所：东北大学摘要：芯片制造技术的改进推动了电子系统的惊人增长，这些系统已融入我们的日常生活。然而，这一趋势正面临着严峻的挑战，使得新兴的纳米技术成为未来芯片制造的必然选择。纳米技术面临的主要挑战是可靠性。与当今芯片中使用的传统器件相比，纳米级器件在制造和使用寿命期间更容易出现故障。缺陷数量的增加对制造良率产生不利影响，对纳米电子行业造成严重的负面经济影响。该项目的重点是一套完全集成的教育和研究活动，以提供高缺陷密度存在的缺陷和容错。为了容忍高缺陷率，缺陷容限，以提高制造产量（制造缺陷）和容错，以确保寿命的可靠性（正常操作期间的错误）集成在纳米技术的设计方法。 目标平台是使用碳纳米管构建的可编程交叉杆纳米架构。自适应和内置的缺陷和容错设计流程，从根本上不同于传统的方法，开发的目标是以极低的成本，以确保高的制造产量和运行时的电路可靠性。电路中内置了缺陷和容错功能，最大限度地减少了与昂贵且耗时的片外设备的通信。此外，所提出的内置缺陷和容错将自动适应制造和运行时缺陷的水平，使其成为广泛的制造工艺，操作环境和应用的最佳选择。

CCF - 0746836 Title: CAREER: Adaptive and Built-in Defect and Fault Tolerance for Crossbar Nano-architecturesPI name:Tahoori, Mehdi B.Inst: Northeastern UniversityABSTRACT:Improvements in chip manufacturing technology have propelled an astonishing growth of electronic systems which are integrated into our daily lives. However, this trend is facing serious challenges, making emerging nanotechnologies inevitable for future chip manufacturing. The major challenge for nanotechnologies is reliability. Nanoscale devices are more likely to fail, both at the manufacturing and during the operating lifetime, compared to traditional devices used in today's chips. Elevated number of defects adversely affects the manufacturing yield, causing a severe negative economic impact on the nanoelectronic industry. This project focuses on a set of fully integrated educational and research activities to provide defect and fault tolerance in the presence of high defect densities. To tolerate high defect rates, defect tolerance to improve the manufacturing yield (for fabrication defects) and fault tolerance to ensure the lifetime reliability (for errors during normal operation) are integrated in the design methodologies for nanotechnologies. The target platform is the programmable crossbar nano-architecture built using carbon nanotubes. Adaptive and built-in defect and fault tolerant design flows, fundamentally different from conventional approaches, are developed in which the objective is to ensure high manufacturing yield and runtime reliability of the circuit at extremely low costs. Defect and fault tolerance are built into the circuit, minimizing the communication with expensive and time-consuming off-chip equipments. Moreover, the proposed built-in defect and fault tolerance will automatically adapt to the level of manufacturing and runtime defects, making them optimal for a wide range of fabrication processes, operation environments, and applications.