CAREER: Understanding and Exploring Performance-Correctness Explicitly Decoupled Architecture

随着处理器微体系结构在过去30年中的发展，设计的复杂性和实现过程中使用的晶体管数量都在不断增加。这种复杂性使得确保在所有转角情况下(逻辑和电气)下的正确操作成为一项更具挑战性的任务。这反过来又转化为微体系结构创新在性能优化方面的实际障碍越来越高，因为正确性是压倒一切的考虑因素。这份职业计划的目标是探索一种新的设计模型，称为性能正确性显式解耦体系结构。从底层开始，设计一种显式去耦合的体系结构，使得性能优化电路是独立于电路的独立实体，以保证功能和正确性。这种明确的分离使性能优化能够真正以仅适用于普通情况的方式进行考虑，从而允许使用在传统的单片微体系结构中被认为不切实际甚至不正确的概率技术。该项目旨在开发洞察力以更好地理解此设计模型，并开发用于性能优化的复杂性有效的微体系结构和软件机制。

As processor microarchitecture has evolved over the past 30 years, both the complexity of the design and the number of transistors used in its realization have escalated. This complexity makes guaranteeing correct operation under all corner cases (logical as well as electrical) an ever more challenging task. This, in turn, translates in to higher and higher practical barriers for microarchitectural innovation for performance optimization as correctness is an overriding consideration. The goal of this CAREER proposal is to explore a new design model called Performance-correctness Explicitly-decoupled Architecture. From ground up, an explicitly-decoupled architecture is designed such that performance optimization circuitry is an independent entity separate from the circuitry guaranteeing functionality and correctness. This explicit separation allows performance optimization to be truly considered in a common-case-only manner, allowing the use of probabilistic techniques considered impractical or even incorrect in a conventional monolithic microarchitecture. This project seeks to develop insights to better understand this design model and develop complexity-effective microarchitectural and software mechanisms for performance optimization.