CAREER: Understanding and Exploring Performance-Correctness Explicitly Decoupled Architecture

职业：理解和探索性能正确性显式解耦架构

• 批准号: 0747324
• 负责人: Michael Huang
• 金额: $ 35万
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-06-01 至 2014-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0747324&HistoricalAwards=false
• 关键词: CAREER; Understanding; Exploring; Performance; Correctness

As processor microarchitecture has evolved over the past 30 years, both the complexity of the design and the number of transistors used in its realization have escalated. This complexity makes guaranteeing correct operation under all corner cases (logical as well as electrical) an ever more challenging task. This, in turn, translates in to higher and higher practical barriers for microarchitectural innovation for performance optimization as correctness is an overriding consideration. The goal of this CAREER proposal is to explore a new design model called Performance-correctness Explicitly-decoupled Architecture. From ground up, an explicitly-decoupled architecture is designed such that performance optimization circuitry is an independent entity separate from the circuitry guaranteeing functionality and correctness. This explicit separation allows performance optimization to be truly considered in a common-case-only manner, allowing the use of probabilistic techniques considered impractical or even incorrect in a conventional monolithic microarchitecture. This project seeks to develop insights to better understand this design model and develop complexity-effective microarchitectural and software mechanisms for performance optimization.

随着处理器微架构在过去30年的发展，设计的复杂性和实现中使用的晶体管数量都在不断增加。这种复杂性使得保证在所有极端情况下（逻辑和电气）的正确操作变得更加具有挑战性。这反过来又转化为性能优化微架构创新的越来越高的实际障碍，因为正确性是压倒一切的考虑因素。这个CAREER提案的目标是探索一种新的设计模型，称为性能正确性显式解耦架构。从底层开始，我们设计了一个显式解耦的架构，使性能优化电路成为一个独立的实体，与保证功能和正确性的电路分离。这种显式的分离使性能优化能够真正地以仅限通用情况的方式进行考虑，从而允许使用在传统的单片微体系结构中被认为不切实际甚至不正确的概率技术。该项目旨在开发洞察力，以更好地理解这种设计模型，并开发复杂性有效的微架构和软件机制，以实现性能优化。