CSR: Small: Towards a Co-Designed Latency-Centric On-Chip Communication Substrate

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As high-performance processor chips continue to integrate more components such as general-purpose cores or special accelerator units, increasing demand for a communication substrate with higher performance and better energy efficiency is evident. Unfortunately, continued device scaling has exacerbated the fundamental challenges facing on-chip metal wires, such as increased loss, delay, dispersion, and cross-talk. Alternatives to the conventional communication schemes are clearly imperative as technology progresses. Existing solutions for off-chip interconnection such as packet-switching networks and optics are finding their way into the on-chip environment. However, these solutions evolve under a different set of constraints and goals in the off-chip environment and are not automatically suitable in the on-chip environment. For instance, a packet-switched interconnect provides scalable throughput, but at significant communication latency and energy costs.This project takes a multidisciplinary approach and explores the design of latency-centric communication substrates based on novel wide-band, pulse-based communication mechanisms and architectural support that dovetails the circuits. Early evidence suggests there are significant potential benefits, including superior latency at sufficiently high throughput and extremely low energy costs. The success of this project can critically impact future microprocessor and other complex system-on-chip design methodology. This project also contributes to the training of students at the intersection of digital and analog circuit and architecture design ? an important area for the future of the technology industry.