CSR: Small: Towards a Co-Designed Latency-Centric On-Chip Communication Substrate

CSR：小：迈向共同设计的以延迟为中心的片上通信基板

• 批准号: 1217662
• 负责人: Michael Huang
• 金额: $ 45万
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1217662&HistoricalAwards=false
• 关键词: CSR; Small; Towards; Co; Designed

As high-performance processor chips continue to integrate more components such as general-purpose cores or special accelerator units, increasing demand for a communication substrate with higher performance and better energy efficiency is evident. Unfortunately, continued device scaling has exacerbated the fundamental challenges facing on-chip metal wires, such as increased loss, delay, dispersion, and cross-talk. Alternatives to the conventional communication schemes are clearly imperative as technology progresses. Existing solutions for off-chip interconnection such as packet-switching networks and optics are finding their way into the on-chip environment. However, these solutions evolve under a different set of constraints and goals in the off-chip environment and are not automatically suitable in the on-chip environment. For instance, a packet-switched interconnect provides scalable throughput, but at significant communication latency and energy costs.This project takes a multidisciplinary approach and explores the design of latency-centric communication substrates based on novel wide-band, pulse-based communication mechanisms and architectural support that dovetails the circuits. Early evidence suggests there are significant potential benefits, including superior latency at sufficiently high throughput and extremely low energy costs. The success of this project can critically impact future microprocessor and other complex system-on-chip design methodology. This project also contributes to the training of students at the intersection of digital and analog circuit and architecture design ? an important area for the future of the technology industry.

随着高性能处理器芯片不断集成更多的组件，如通用核心或特殊加速器单元，对具有更高性能和更好能效的通信基板的需求不断增加是显而易见的。不幸的是，持续的器件缩放加剧了片上金属线面临的基本挑战，例如损耗、延迟、色散和串扰的增加。随着技术的进步，传统通信方案的替代方案显然势在必行。片外互连的现有解决方案，如分组交换网络和光学，正在寻找进入片内环境的途径。然而，这些解决方案在片外环境中是在一组不同的约束和目标下发展的，并不能自动适用于片内环境。例如，分组交换互连提供了可扩展的吞吐量，但具有显著的通信延迟和能源成本。该项目采用多学科方法，探索基于新型宽带、基于脉冲的通信机制和与电路相吻合的架构支持的以延迟为中心的通信基板的设计。早期的证据表明，有显著的潜在好处，包括在足够高的吞吐量和极低的能源成本下的优越延迟。该项目的成功将对未来的微处理器和其他复杂的片上系统设计方法产生重大影响。这个项目也有助于培养学生在数字和模拟电路和建筑设计的交叉点。这是未来科技产业的重要领域。