EMT/NANO: Co-Exploration of Device and System Architecture for Quantum NanoElectronics

EMT/NANO：量子纳米电子器件和系统架构的共同探索

• 批准号: 0829926
• 负责人: VIJAYKRISHNAN NARAYANAN
• 金额: $ 20万
• 依托单位: Pennsylvania State Univ University Park
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0829926&HistoricalAwards=false
• 关键词: EMT; NANO; Co; Exploration; Device

Project SummaryObjectives: The objective of our proposal is co-exploration of simulation and design of single or few electron nanoscale quantum devices into binary decision diagram based reconfigurable logic architectures for realization of robust, ultra-low power computing systems. The approach is based on split-gate quantum nanodots as the decision node elements while incorporating functional reconfigurability. This research will primarily focus on the device architecture design to demonstrate its viability in realizing logic architectures with sufficient logic depth, functional robustnesss, and energy delay product approaching the quantum limit.Intellectual merit: Key contributions expected from this research are: 1) Simultaneous design and optimization of nanoscale quantum devices to implement system level logic architecture operating with record power-delay product approaching the quantum limit of kT/q*ln(2) 2) Detailed quantum simulations of single and cascaded devices to facilitate design of reconfigurable BDD-based logic circuits for achieving reliable ultra low power operation. The proposed research is transformative since it will expand our fundamental understanding of physics and operation of compound semiconductor based nanodevices in restricted geometries in novel multiple gate configurations, as well as design and implementation of energy efficient reconfigurable BDD logic architectures.Broader Impact: The results from this research will foster new directions at the intersection of material science, electrical engineering and computer engineering extending mesoscopic devices to logic architectures. The proposed research directly addresses the ongoing quest in the semiconductor industry for longer term solutions to energy efficient technology scaling. Undergraduate and graduate students, involved in this research, will get versatile training in cross-disciplinary areas in preparation of their careers in the burgeoning nanoelectronics industry. The device models, nanofabrication techniques and design methodologies developed will be used in creating courseware which will be available through our website for use by other educators, researchers and industrial practitioners.

项目概要目标：我们的建议的目的是共同探索的模拟和设计的单电子或几个纳米级量子器件到二进制决策图为基础的可重构逻辑架构，实现强大的，超低功耗的计算系统。该方法是基于分裂门量子纳米点作为决策节点元素，同时结合功能的可重构性。这项研究将主要集中在器件架构设计，以证明其在实现具有足够逻辑深度、功能鲁棒性和接近量子极限的能量延迟积的逻辑架构方面的可行性。智力价值：预计这项研究的主要贡献是：1）同时设计和优化纳米级量子器件以实现以记录功率操作的系统级逻辑架构-延迟积接近量子极限kT/q*ln（2）2）单个和级联器件的详细量子模拟，以便于设计用于实现可靠的超低功率操作的可重配置的基于BDD的逻辑电路。拟议的研究是变革性的，因为它将扩大我们的基本理解的物理和操作的化合物半导体为基础的纳米器件在有限的几何形状在新颖的多门配置，以及设计和实施节能可重构BDD逻辑架构。这项研究的结果将在材料科学，电子工程和计算机工程将介观器件扩展到逻辑架构。拟议的研究直接解决了半导体行业对节能技术扩展的长期解决方案的持续追求。参与这项研究的本科生和研究生将获得跨学科领域的多功能培训，为他们在新兴的纳米电子行业的职业生涯做准备。开发的设备模型，纳米制造技术和设计方法将用于创建课件，这些课件将通过我们的网站提供给其他教育工作者，研究人员和工业从业者使用。