HoDoo: Holistic Design of On-chip Interconnects

在同一芯片上集成多个核心标志着以通信为中心的系统的开始，而不是以计算为中心的系统的开始。此外，技术趋势强调了具有互连意识的设计的重要性，因为在新技术中，全球线路延迟的缩减速度不如栅极延迟。因此，片上网络(OCNs)，也被称为片上网络(NoCs)，将成为设计嵌入式系统芯片(SoC)体系结构和高性能多核体系结构的主要瓶颈。然而，由于OCNs严格的资源约束和技术扩展缺陷，设计可扩展、高性能、能量和热效率高且可靠的片上网络本身就更加复杂。本研究旨在发展一套完整的设计范型，以探索片上网路设计空间。首先，将开发一个模拟平台，以了解应用程序、系统架构和片上互连之间的相互影响。其次，考虑到工艺规模的影响，对高性能、高能效和高可靠性的片上互连进行设计和分析。第三，将探索使用新兴的3D芯片技术进行片上互连设计。这项研究的成功可能会对下一代多核/SoC体系结构的设计产生重大影响，并在多核计算的几个领域培育新的研究方向，这有望成为未来高性能体系结构的主要设计范例。

The integration of multiple cores on the same chip has signaled the beginning of communication-centric, rather than computation-centric systems. Further, technology trends have accentuated the importance of interconnect-conscious design as global wire delays do not scale down as fast as gate delays in new technologies. Consequently, on-chip networks (OCNs), also called Networks-on-Chip (NOCs), are predicted to be a major bottleneck in designing embedded System-on-Chip (SoC) architectures and high performance multicore architectures alike. However, the design of scalable, high performance, energy and thermal efficient and reliable on-chip networks is inherently more complex because of the stringent resource constraints and technology scaling artifacts of OCNs. The proposed research is aimed at developing a holistic design paradigm for exploring the on-chip network design space.The research addresses three major issues. First, a simulation platform will be developed to understand the interplay between applications, system architecture and on-chip interconnects. Second, design and analysis of high performance, energy and thermal efficient and reliable on-chip interconnects considering the impacts of technology scaling will be investigated. Third, design of on-chip interconnects using emerging 3D chip technology will be explored. The success of this research is likely to have a significant influence on the design of next generation multicore/SoC architectures and in fostering new research directions in several areas of multicore computing, which is expected to be the predominant design paradigm for future high performance architectures.