SHF: Small: Leveraging Monolithic 3D for Architectural Innovations

SHF：小型：利用整体 3D 进行建筑创新

• 批准号: 2008365
• 负责人: VIJAYKRISHNAN NARAYANAN
• 金额: $ 50万
• 依托单位: Pennsylvania State Univ University Park
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-06-15 至 2024-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008365&HistoricalAwards=false
• 关键词: SHF; Small; Leveraging; Monolithic; 3D

The design of more efficient processors is a major driving force of the computing industry. Over multiple decades, reducing the size of transistors, which are the building blocks of microprocessors, has been the main driver for efficiency improvements. With this trend of transistor shrinking nearing the physical limit, this research explores three-dimensional chips, where transistors are stacked in multiple layers, as an alternate approach to enhance efficiency. A major challenge with three-dimensional chips is the large dimension of the connections compared to the transistor itself. This project will leverage a new technology called monolithic three-dimensional design (M3D), where inter-layer connections are of dimensions similar to that of a transistor. This research will result in new M3D-based designs for microprocessors that reduce energy and time consumed in interconnections, and enable new functional features for microprocessors. The project will also enhance the national workforce development efforts by training undergraduate, graduate and underrepresented groups in a much-needed area of semiconductor electronics. This project will involve synergistic exploration of process technology and M3D-based architectural design spaces of processors towards achieving transformational impact on processor and accelerator performance. The research will first develop a simulation infrastructure that enables systematic exploration of the space by varying the architectural and technology parameters. Leveraging the simulation infrastructure, this project will perform the following tasks: (1) evaluation of layer-wise partitioning of processor core and cache structures; (2) design of primitive compute functions for integration with the cache memories; (3) design of M3D-enabled application-specific accelerators; and (4) integration of heterogeneous memory technologies to provide support for power efficiency.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

设计更高效的处理器是计算行业的主要驱动力。几十年来，减小作为微处理器构建模块的晶体管的尺寸一直是提高效率的主要驱动力。随着晶体管缩小的趋势接近物理极限，这项研究探索了三维芯片，其中晶体管堆叠在多层中，作为提高效率的替代方法。三维芯片的一个主要挑战是与晶体管本身相比，连接的尺寸很大。该项目将利用一种称为单片三维设计（M3 D）的新技术，其中层间连接的尺寸与晶体管的尺寸相似。这项研究将为微处理器带来新的基于M3 D的设计，减少互连所消耗的能量和时间，并为微处理器提供新的功能特性。该项目还将通过在半导体电子这一急需的领域培训本科生、研究生和代表性不足的群体，加强国家劳动力发展工作。该项目将涉及对处理器的工艺技术和基于M3 D的架构设计空间的协同探索，以实现对处理器和加速器性能的变革性影响。该研究将首先开发一个模拟基础设施，通过改变建筑和技术参数来系统地探索空间。利用仿真基础设施，该项目将完成以下任务：（1）评估处理器核心和高速缓存结构的分层划分;（2）设计与该高速缓存存储器集成的基本计算功能;（3）设计支持M3 D的特定应用加速器;以及（4）该奖项反映了NSF的法定使命，并通过使用基金会的学术价值和更广泛的影响审查标准。

项目成果

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

适用于内存计算应用的紧凑型铁电可编程多数门

• DOI: 10.1109/iedm45625.2022.10019400
• 发表时间: 2022
• 期刊: 2022 International Electron Devices Meeting (IEDM
• 作者: Deng, Shan;Benkhelifa, Mahdi;Thomann, Simon;Faris, Zubair;Zhao, Zijian;Huang, Tzu-Jung;Xu, Yixin;Narayanan, Vijaykrishnan;Ni, Kai;Amrouch, Hussam
• 通讯作者: Amrouch, Hussam

CAPE: A Content-Addressable Processing Engine

CAPE：内容可寻址处理引擎

• DOI: 10.1109/hpca51647.2021.00054
• 发表时间: 2021
• 期刊: IEEE Int'l Symp. on High-Performance Computer Architecture (HPCA
• 作者: Caminal, Helena;Yang, Kailin;Srinivasa, Srivatsa;Ramanathan, Akshay Krishna;Al-Hawaj, Khalid;Wu, Tianshu;Narayanan, Vijaykrishnan;Batten, Christopher;Martinez, Jose F.
• 通讯作者: Martinez, Jose F.

An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy

• DOI: 10.1109/iscas48785.2022.9937438
• 发表时间: 2022-05
• 期刊: 2022 IEEE International Symposium on Circuits and Systems (ISCAS)
• 作者: Jianfeng Wang;Nuo Xiu;Juejian Wu;Yiming Chen;Yanan Sun;Huazhong Yang;N. Vijaykrishnan;Sumitha George;Xueqing Li

FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge

• DOI: 10.1109/tcsi.2023.3251961
• 发表时间: 2023-06
• 期刊: IEEE Transactions on Circuits and Systems I: Regular Papers
• 作者: Wenjun Tang;Ming-En Lee;Juejian Wu;Yixin Xu;Yao Yu;Yongpan Liu;Kai Ni;Yu Wang;Huazhong Yang;V. Narayanan;Xueqing Li

Ferroelectric-based Accelerators for Computationally Hard Problems

用于解决计算难题的铁电加速器

• DOI: 10.1145/3453688.3461745
• 发表时间: 2021
• 期刊: GLSVLSI '21: Proceedings of the 2021 on Great Lakes Symposium on VLSI
• 作者: Bashar, Mohammad Khairul;Vaidya, Jaykumar;Surya Kanthi, R. S.;Lee, Chonghan;Shi, Feng;Narayanan, Vijaykrishnan;Shukla, Nikhil
• 通讯作者: Shukla, Nikhil