Optimization of Test and Diagnosis Infrastructure for Multicore Chips

点击翻译按钮获取中文摘要

CCF - 0903392 Optimization of Test and Diagnosis Infrastructure for Multicore ChipsChakrabarty, Krishnendu Duke University ABSTRACTThe emergence of multicore integrated circuits offers continued technological advances in computing through the on-chip integration of processors, graphics accelerators, memories, and other types of cores. Test solutions are needed to reduce cost and defect escapes, and to facilitate repair and reconfiguration through diagnosis. This project is therefore directed at new methods for comprehensive defect screening, optimization techniques for test delivery, and diagnosis flows to quickly identify faulty cores. It is structured around the following topics: (i) generation of high-quality tests to augment core-level patterns, including tests for power-management structures and clock-domain boundaries, and tests for the interconnect fabric and interfaces to the cores; (ii) theory and optimization tools for utilizing the interconnection fabric for test-data transportation; (iii) optimization methods to reduce the time needed for identifying faulty cores and clock domains. The project is being carried out in collaboration with partners at Intel and AMD.This project will reduce test cost and defect levels, and lead to higher shipped-product quality for multicore-based systems. The test infrastructure will facilitate in-field testing, diagnosis, and dynamic reconfiguration through the use of spare cores. Resulting benefits for society include cheaper and reliable computing platforms for a wide range of applications. Undergraduate and graduate students will be prepared for the semiconductor industry. SRC Master?s Scholarships and PhD Fellowships will be used as recruitment tools, especially for under-represented groups. Tutorials at conferences and lectures at IEEE/ACM Chapters worldwide will lead to broad dissemination of research results.