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CSR:Small:Efficient and Predictable Memory Hierarchies for High-Performance Embedded Systems

CSR:Small:Efficient and Predictable Memory Hierarchies for High-Performance Embedded Systems
CSR:小型:高性能嵌入式系统的高效且可预测的内存层次结构
批准号:
0915503
负责人:
Yan Solihin
金额:
$44.97万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-09-01 至 2014-08-31

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中文摘要
翻译
0915503CSR:小:高性能嵌入式系统的高效和可预测的存储器层次结构摘要高端嵌入式系统越来越多地用于复杂的计算,如高级图像处理和语音处理。这种复杂的任务通常涉及不规则的数据结构,例如链接数据结构,或者即使对于规则的数据结构也表现出不规则的访问模式。由于难以确定将来将访问的地址,因此管理用于此类任务的暂存存储器变得越来越具有挑战性。 对于这种复杂的应用程序,硬件管理的存储(缓存)可以执行相对较好,而无需太多的编程工作。然而,高速缓存不提供所需的可预测性,以获得一个紧密的最坏情况下的执行时间(WCET)的限制在实时系统中,由于其动态行为,是难以预测的编译时。该项目的目标是探索一种新的智能实时缓存,它提供了方便的存储管理,以及允许程序控制缓存行为与低开销,提供可预测性,支持真实的时间分析。这项工作包括:(1)指令和体系结构支持,提供原语以低开销控制高速缓存行为,(2)开发编译时分析和运行时支持以支持新的高速缓存,以及(3)所提出的系统的概念验证。改进的内存性能和可预测性将使计算机系统更高效,使更具挑战性的问题得以解决,并提高现有应用程序的能源效率。该项目还将向本科生和高中生宣传工程对社会的价值,并吸引更多的学生进入该领域。它还将通过出版物和工具发布传播研究成果,使公众受益。
英文摘要
0915503CSR:Small:Efficient and Predictable Memory Hierarchies for High-Performance Embedded SystemsAbstractHigh-end embedded systems are increasingly used for complex computation, such as advanced image processing and speech processing. Such complex tasks often involve irregular data structures such as linked data structures, or exhibit irregular access patterns even with regular data structures. Managing scratchpad memory for such tasks becomes increasingly challenging due to the difficulty of determining addresses that will be accessed in the future. For such complex applications, hardware-managed storage (caches) can perform relatively well without much programming effort. However,caches do not offer predictability required to derive a tight worst case execution time (WCET) bound in real-time systems, due to their dynamic behavior that is difficult to predict at compile time. The goal of the project is to explore a new intelligent real-time cache, which offers ease of storage management as well as allows programs to control caching behavior with low overheads, providing predictability that supports real time analysis. The work consists of: (1) Instruction and architecture support that provides primitives to control cache behavior with low overheads, (2)Development compile-time analysis and run-time support to support the new cache, and (3)Proof-of-concept of the proposed system. Improved memory performance and predictability will be to make computer systems more efficient, enable more challenging problems to be solved, and improve energy-efficiency of existing applications. This project will also extend outreach to undergraduate and high-school students about the value of engineering to society and attract more students into the field. It will also benefit the public by disseminating research results through publications and tool releases.
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会议论文
Collaborative Research: CSR: Medium: Scaling Secure Serverless Computing on Heterogeneous Datacenters
Collaborative Research: CNS Core: Medium: Understanding and Strengthening Memory Security for Non-Volatile Memory
Collaborative Research: PPoSS: Planning: Scaling Secure Serverless Computing on Hetergeneous Datacenters
SHF: Small: Collaborative Research: Efficient Memory Persistency for GPUs
国内基金
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