SHF: Small: Leveraging the Interplay between Process Variation and NBTI in Nanoscale Reliable NoC Architecture Design

SHF：小型：在纳米级可靠 NoC 架构设计中利用工艺变化和 NBTI 之间的相互作用

• 批准号: 0916384
• 负责人: Tao Li
• 金额: $ 40.71万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2014-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0916384&HistoricalAwards=false
• 关键词: SHF; Small; Leveraging; Interplay; between

The trend towards multi-/many- core design has made network-on-chip (NoC) a crucial hardware component of future microprocessors. With the continuous down-scaling of CMOS processing technologies, reliability is becoming a primary target in NoC design. Negative Bias Temperature Instability (NBTI) is a critical reliability threat for deep sub-micrometer CMOS technologies. NBTI increases the PMOS transistor threshold voltage and reduces the drive current, causing failures in logic circuits and storage structures due to timing violations or minimum voltage limitations. Meanwhile, process variation (PV) - the divergence of transistor process parameters from their design specifications - caused by the difficulty in controlling sub-wavelength lithography and channel doping as CMOS manufacturing technology scales, results in variability in circuit performance/power and has become a major challenge in the design and fabrication of future microprocessors and NoCs. Since NBTI and PV affect both NoC delay and power, it is imperative to address these challenges at the NoC architecture design stage to ensure its efficiency as the underlying CMOS fabrication technologies continue to scale. The goal of this project is to develop techniques for designing novel, cost-effective router microarchitectures and adaptive routing schemes that mitigate NBTI and PV impact on NoCs by leveraging the interplay between the two. The scalability and sustainability of future many-core processors crucially depend on the dependability of NoCs. Mechanisms that can simultaneously tolerate PV and NBTI will be investigated for enhancing the reliability of NoCs fabricated using nanoscale transistor technologies. The educational and outearch activities include recruiting graduate and undergraduate students from under-represented groups for this project and integration of research and education.

多核/多核设计的趋势使得片上网络（NoC）成为未来微处理器的关键硬件组件。随着CMOS工艺的不断缩小，可靠性成为NoC设计的主要目标。负偏置温度不稳定性（NBTI）是深亚微米CMOS工艺可靠性的重要威胁。NBTI增加PMOS晶体管阈值电压并降低驱动电流，从而由于时序违规或最小电压限制而导致逻辑电路和存储结构中的故障。同时，工艺变化（PV）-晶体管工艺参数与其设计规范的偏离-由于CMOS制造技术规模化而难以控制亚波长光刻和沟道掺杂而引起，导致电路性能/功率的可变性，并且已经成为未来微处理器和NoC的设计和制造中的主要挑战。由于NBTI和PV影响NoC延迟和功耗，因此必须在NoC架构设计阶段解决这些挑战，以确保其效率，因为底层CMOS制造技术不断扩展。该项目的目标是开发用于设计新颖的，具有成本效益的路由器微架构和自适应路由方案的技术，通过利用两者之间的相互作用来减轻NBTI和PV对NoC的影响。未来众核处理器的可扩展性和可持续性关键取决于NoC的可靠性。同时容忍PV和NBTI的机制将被研究，以提高使用纳米晶体管技术制造的NoCs的可靠性。教育和外联活动包括为该项目招募代表性不足的群体的研究生和本科生以及研究和教育的整合。