CAREER: Power Aware Scheduling for Real-Time Embedded Systems

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Power consumption, which has increased dramatically with IC technology advancement and system complexity, has become a critical issue in design of more complicated, versatile, and reliable systems. The International Roadmap for Semiconductors (ITRS) report estimates that a 20-times dynamic power consumption gap and as much as 800-times standby power consumption gap for portable devices need to be closed by the year 2016. Left unchecked, power consumption will curtail the feasibility of future advanced real-time embedded systems. This NSF CAREER research project is leveraging current operating system functionality to support real-time and power-aware computation that can meet the increasingly stringent timing and power/energy constraints for advanced real-time and embedded applications. In particular, this research is developing innovative scheduling techniques and decision functions that can exploit hardware capabilities and make proper tradeoffs. These techniques are based on knowledge of hardware infrastructure features and the intentions of applications, as communicated through the operating system layer. The expected impact of this research lies in its promise to alleviate the inadequacy and inefficiency of power and energy conservation in todays real-time embedded applications. Such applications are of great economic importance. They already prevalent and are becoming increasingly pervasive. Through experimental, application-based research, this project seeks to validate and provide sound studies of its theoretical system-level power reduction techniques under practical scenarios such as automotive electronics. Integration of research and education is carried out under this CAREER project via the course development, graduate/undergraduate student mentoring, out-reach, and dissemination of results. The project offers hands-on learning opportunities for pre-college, undergraduate, and graduate students.