SBIR Phase I: Design for Manufacturability Rule Evaluation using Test Measurement Data

SBIR 第一阶段：使用测试测量数据进行可制造性规则评估设计

• 批准号: 1013959
• 负责人: Ronald Blanton
• 金额: $ 10万
• 依托单位: TestWorks, Inc.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-07-01 至 2011-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1013959&HistoricalAwards=false
• 关键词: SBIR; Phase; Design; Manufacturability; Rule

This Small Business Innovation Research (SBIR) Phase 1 project will use normally-available data produced by failing integrated circuits (ICs) to evaluate the capability of design-for-manufacturability (DFM) rules and guidelines to ensure reliable, working ICs. All ICs employ DFM rules and guidelines that are constraints that prevent or limit the use of certain physical structures within the IC. Such structures are constrained since they are difficult to manufacture implying they have a less-than-acceptable likelihood for causing chip failure. Thus DFM is meant to ensure ICs yield at acceptable levels. Deployment of DFM does have a cost however since its application requires the use of complex design tools that typically require weeks of compute time to check for design compliance. Moreover, performance degradation results when the IC is modified to satisfy DFM constraints. While the costs of DFM are clear, there is however no direct way of measuring DFM effectiveness. In other words, how well a specific rule or guideline actually ensures yield is an open question. This SBIR project will develop and implement software that analyzes the design data and tester data from failing ICs to directly measure the effectiveness DFM rules/guidelines.The broader impact/commercial potential of this project is that it will enable chip designers and manufacturers to employ only those DFM rules/guidelines that are actually effective. This means that chip yield will improve since the overall design will be more manufacturable, chip quality will improve since systematic failures that are more likely to escape detection will be reduced, chip design cost will decrease since the time needed to deploy DFM will be reduced since only the effective rules will be used, and chip performance will improve since the design will be altered less since only the most effective rules will be used.

该小型企业创新研究（SBIR）第1阶段项目将使用故障集成电路（IC）产生的正常可用数据来评估可制造性设计（DFM）规则和指南的能力，以确保可靠的工作IC。所有IC都采用DFM规则和指导方针，这些规则和指导方针是防止或限制在IC内使用某些物理结构的约束。这种结构受到限制，因为它们难以制造，这意味着它们具有小于可接受的导致芯片故障的可能性。因此，DFM是为了确保IC产量在可接受的水平。然而，DFM的部署确实有成本，因为其应用程序需要使用复杂的设计工具，通常需要数周的计算时间来检查设计合规性。此外，当IC被修改以满足DFM约束时，性能下降。 虽然可持续财务管理的成本是明确的，但没有直接的方法来衡量可持续财务管理的有效性。换句话说，具体的规则或指导方针实际上如何确保产量是一个悬而未决的问题。该SBIR项目将开发和实施软件，用于分析故障IC的设计数据和测试数据，以直接衡量DFM规则/指南的有效性。该项目更广泛的影响/商业潜力在于，它将使芯片设计师和制造商能够只采用那些实际有效的DFM规则/指南。这意味着芯片产量将提高，因为整体设计将更可制造，芯片质量将提高，因为更可能逃脱检测的系统故障将减少，芯片设计成本将降低，因为部署DFM所需的时间将减少，因为仅使用有效规则，并且由于仅使用最有效的规则而较少地改变设计，因此芯片性能将得到改善。