SHF: Small: Confidence in Manycore/Multi-Core Modeling and Simulation

SHF：小：对众核/多核建模和仿真的信心

• 批准号: 1016285
• 负责人: Thomas Conte
• 金额: $ 45万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-01 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1016285&HistoricalAwards=false
• 关键词: SHF; Small; Confidence; Manycore; Multi

Computer designers use techniques to accelerate the simulation of their new computer designs while ignoring the errors of the acceleration methods. This is common because the entire simulation of modern computer programs is intractable. Basing the performance of a design only on fragments of program execution can yield results that are misleading, and result in far from optimal computer hardware designs. Without bounds on confidence, the relative performance of two architectures is impossible to compare with any statistical validity. For computer design to advance to an engineering science with reproducible results, the status quo must change. This research remedies the situation by introducing confidence bounding to fast manycore simulation.The Georgia Tech research team has made significant and lasting contributions to adding confidence to single-threaded processor simulation, and is adapting and discovering new techniques for the manycore simulation. The team is investigating several approaches to thread slip problem (where the relative execution order of threads is unknown at the start of the simulation of a cluster of events) and are developing models that can be used by designers. Another class of problems is state reconstruction problems unique to manycore simulation. For example, global ordering of thread executions and their sharing patterns greatly impact the coherence state of cache blocks. Coherence information, in addition to directory contents, indicate the current owner of a line, which must be reconstructed for measured cache latencies and interconnect network flow to be representative of unsampled execution. Other specific problems involve recovering the directory state, the state of the interconnection network (e.g., flit buffers, conflicts for routes, etc), and cache state.

计算机设计人员使用技术来加速他们的新计算机设计的仿真，同时忽略加速方法的误差。这是常见的，因为现代计算机程序的整个模拟是棘手的。仅根据程序执行的片段来设计性能可能会产生误导性的结果，并导致远离最佳计算机硬件设计。如果没有置信度的限制，两种架构的相对性能就不可能与任何统计有效性进行比较。为了使计算机设计发展成为一门具有可重复结果的工程科学，必须改变现状。本研究通过将置信度边界引入到快速众核仿真中来补救这种情况。格鲁吉亚理工学院的研究团队为单线程处理器仿真增加置信度做出了重大而持久的贡献，并且正在适应和发现众核仿真的新技术。该团队正在研究线程滑动问题的几种方法（其中线程的相对执行顺序在一组事件的模拟开始时是未知的），并正在开发可供设计人员使用的模型。 另一类问题是众核仿真所特有的状态重构问题。 例如，线程执行的全局排序及其共享模式极大地影响高速缓存块的一致性状态。 除了目录内容之外，一致性信息还指示行的当前所有者，其必须被重构以用于测量的高速缓存延迟和互连网络流以表示未采样的执行。 其他具体问题涉及恢复目录状态、互连网络的状态（例如，微片缓冲区、路由冲突等）和高速缓存状态。