课题基金 / 基金详情

SHF: Small: Confidence in Manycore/Multi-Core Modeling and Simulation

SHF: Small: Confidence in Manycore/Multi-Core Modeling and Simulation
SHF:小:对众核/多核建模和仿真的信心
批准号:
1016285
负责人:
Thomas Conte
金额:
$45.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2010
资助国家:
美国
项目状态:
已结题
起止时间:
2010-08-01 至 2013-07-31

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中文摘要
翻译
计算机设计者利用技术来加速他们的新计算机设计的仿真,而忽略了加速方法的误差。这很常见,因为现代计算机程序的整个模拟是难以处理的。将设计的性能仅仅建立在程序执行的片段上可能会产生误导的结果,并导致远离最佳的计算机硬件设计。如果没有置信度的限制,两种体系结构的相对性能就不可能与任何统计有效性进行比较。为了使计算机设计发展成为一门具有可重复性结果的工程科学,必须改变现状。本研究通过在快速多核模拟中引入置信度边界来解决这一问题。佐治亚理工学院的研究团队为增加对单线程处理器模拟的信心做出了重大而持久的贡献,并且正在适应和发现多核模拟的新技术。该团队正在研究线程滑移问题的几种方法(线程的相对执行顺序在一组事件的模拟开始时是未知的),并正在开发可供设计人员使用的模型。另一类问题是多核仿真特有的状态重构问题。例如,线程执行的全局排序及其共享模式极大地影响缓存块的一致性状态。除了目录内容之外,一致性信息还指示了线路的当前所有者,为了代表未采样的执行,必须对测量的缓存延迟和互连网络流进行重构。其他具体问题包括恢复目录状态、互连网络的状态(例如,flit缓冲区、路由冲突等)和缓存状态。
英文摘要
Computer designers use techniques to accelerate the simulation of their new computer designs while ignoring the errors of the acceleration methods. This is common because the entire simulation of modern computer programs is intractable. Basing the performance of a design only on fragments of program execution can yield results that are misleading, and result in far from optimal computer hardware designs. Without bounds on confidence, the relative performance of two architectures is impossible to compare with any statistical validity. For computer design to advance to an engineering science with reproducible results, the status quo must change. This research remedies the situation by introducing confidence bounding to fast manycore simulation.The Georgia Tech research team has made significant and lasting contributions to adding confidence to single-threaded processor simulation, and is adapting and discovering new techniques for the manycore simulation. The team is investigating several approaches to thread slip problem (where the relative execution order of threads is unknown at the start of the simulation of a cluster of events) and are developing models that can be used by designers. Another class of problems is state reconstruction problems unique to manycore simulation. For example, global ordering of thread executions and their sharing patterns greatly impact the coherence state of cache blocks. Coherence information, in addition to directory contents, indicate the current owner of a line, which must be reconstructed for measured cache latencies and interconnect network flow to be representative of unsampled execution. Other specific problems involve recovering the directory state, the state of the interconnection network (e.g., flit buffers, conflicts for routes, etc), and cache state.
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SHF: Small: Parallel Pattern Driven Adaptive Manycore Computer Architectures
  • 批准号:
    1217434
  • 项目类别:
    Standard Grant
  • 资助金额:
    $40.0万
  • 财政年份:
    2012
  • 负责人:
    Thomas Conte
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I/UCRC: Collaborative Research: An Interactive Situational Awareness Simulation - A View from the Clouds
  • 批准号:
    1031999
  • 项目类别:
    Standard Grant
  • 资助金额:
    $6.0万
  • 财政年份:
    2010
  • 负责人:
    Thomas Conte
  • 依托单位:
Collaborative Research: Establishing a Center for Hybrid Multicore Productivity Research
  • 批准号:
    0934114
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $27.5万
  • 财政年份:
    2009
  • 负责人:
    Thomas Conte
  • 依托单位:
Confidence in Computer Architecture Modeling and Simulation
  • 批准号:
    0540982
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $15.09万
  • 财政年份:
    2005
  • 负责人:
    Thomas Conte
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