SHF: Small: Parallel Pattern Driven Adaptive Manycore Computer Architectures

过去的十年重新定义了计算机设计的各个方面。无论应用程序是高性能处理器还是通用处理器，都需要在面对设备限制、带宽限制和功率限制的情况下，通过并行性来提高性能。芯片上的面积现在“几乎是免费的”，而功率和带宽是宝贵的商品。最近的研究提出了许多解决这一问题的方法，包括异构架构、专用功能单元、可重构核心和3d集成。然而，在这十年中，计算机设计者必须在设计限制内工作，其中不是所有的芯片都可以同时打开。计算机设计人员必须找到一种方法，根据它们的体系结构需求对程序进行分类，并为每种分类找到最佳配置。这种需求，再加上并行算法不断增加的多样性，提出了一个挑战：找到对程序员和架构师都有意义的计算“形状”。它还提出了为每个计算分类设计体系结构的挑战。本项目将通过检测算法级并行编程模式，探索使用这些模式的分类系统，并提出对每种模式有益的计算机功能来解决这个重要问题。我们将设计一个基于模式的动态体系结构，其中包括特定于模式的硬件优化，这些优化仅在需要时才启用。对于检测，我们将研究程序员提供的推理检测以及在线动态检测。这项活动将促进教学、培训和学习。该项目的目标是通过REU活动和选择参与该项目的研究生，让代表性不足的群体参与进来。这项研究的结果将通过高知名度的会议论文集、科学期刊和互联网广泛传播。由于我们坚信并行模式将在未来推动计算机设计，因此我们建议开发PatternBench，这是一个封装了所有可能的并行模式空间的基准套件。我们的计划是使这个基准套件可用，以帮助传播这项研究。这项工作对社会的广泛影响是使未来的计算机更节能，并允许在新时代继续进行性能扩展。

The past decade has redefined the path of computer design in all aspects of computing. Whether the application is high-performance or general-purpose processors, the push is for improved performance through parallelism in the face of device constraints, bandwidth constraints, and power constraints. Area on chip is now "virtually free," while power and bandwidth are precious commodities. Recent research has proposed many approaches to tackling this problem, including heterogeneous architectures, specialized function units, reconfigurable cores and 3D-integration. However, this decade, computer designers must work within the design constraints wherein not all of the chip can be turned on simultaneously. Computer designers must find a way to classify programs by their architectural needs, and find the best configurations for each classification. This need, combined with the increased diversity in parallel algorithms, presents a challenge: finding "shapes" of computation that are meaningful both to the programmer and architect. It also presents the challenge of designing architectures for each computational classification. This project will tackle this important problem by detecting algorithmic level parallel programming patterns, exploring a classification system using these patterns, and proposing computer features that are beneficial for each pattern. We will design a pattern-based dynamic architecture that includes pattern-specific hardware optimizations that are in turn enabled only when needed. For detection, we will investigate both programmer supplied inference detection as well as online dynamic detection. This activity will promote teaching, training, and learning. It will be a goal of this project to involve the participation of underrepresented groups both through REU activities and through the selection of the graduate student involved in this project. The results of this research will be disseminated broadly via high-profile conference proceedings, scientific journals and via the Internet. Since we believe strongly that parallel patterns will drive computer design in the future, we propose developing PatternBench, a benchmark suite that encapsulates the space of all possible parallel patterns. Our plan is to make this benchmark suite available to aid in dissemination of this research. The broader impact to society of this work is to make future computers more power-efficient and to allow for continued performance scaling in the new era.