RIA: Fast Simulation of Computer Architectures Using Field-Programmable Gate Arrays as Hardware Accelerators

本研究以现场可程式闸阵列为硬体加速器，进行架构层级的模拟。 本研究的目标包括开发一个范式的架构规范，这是通用的，可以用来产生快速，高效的模拟器，开发一个图形用户界面为基础的入口工具，开发工具的自动翻译的架构描述FPGA编程信息，并实现跟踪驱动的执行环境来运行模拟。 这项工作背后的关键思想是使用FPGA来模拟门级以上的系统，包括事件、依赖关系、资源和延迟。 FPGA对硬件实现的数据结构的大小进行了限制，这些数据结构将通过软件监视器进行扩展，以允许虚拟的无限长度的结构。 模拟将自动翻译从一个高层次的描述，通过使用的方法，从高层次的综合和C程序的编译。 为了帮助输入建筑描述，将开发一个图形用户界面工具。 系统描述的范例将基于系统行为的离散事件体系结构模型。 这种模式将是分层的，并提供了一个库，利用现有的高速缓存和处理器模拟的快速模拟技术。

This research is on architectural-level simulation using field- programmable gate arrays as hardware accelerators. The goals of this research include the development of a paradigm for architectural specification that is both general-purpose and can be used to produce fast and efficient simulators, development of a graphical user interface-based entry tool, development of tools for automatic translation of an architectural description to FPGA programming information, and implementation of a trace-driven execution environment to run the simulations. The key idea behind this work is to use FPGA's to simulate a system above the gate level, at the level of events, dependencies, resources and delays. FPGA's place a limit on the size of the hardware-implemented data structures, which will be extended via a software monitor to allow virtual, unlimited-length structures. The simulation will be automatically translated from a high-level description by use of methods adapted from high-level synthesis and the compilation of C programs. To aid in entering the architectural description, a graphical user interface tool will be developed. The paradigm for system description will be based on a discrete-event architectural model of system behavior. This paradigm will be hierarchical and provide a library that takes advantage of existing fast simulation techniques for cache and processor simulation.