SHF: Small: Parallel Unified Linear algebra with Systolic ARrays (PULSAR)

在传统处理器设计达到功率极限七年多之后，极端规模计算科学到100千万亿次浮点(Pflp/S)系统的道路看起来从未像现在这样陡峭，研究人员曾希望在未来十年中期使用这种系统。在当前的高性能计算(HPC)系统上，“应用程序-体系结构性能差距”，即理论峰值性能与完全应用程序实现的性能之间的差距已经很大。但随着时钟频率现在被限制在4 GHz以下并呈下降趋势，关键领域(如存储器访问、总线、系统互连)的延迟预计将保持相对停滞，而软件并行度需要增加至少三个数量级才能有效利用100个触发器/S系统预计包含的数万个处理器和数以百万计的内核，现在有理由担心，不断扩大的应用程序体系结构性能差距将使此类系统无法使用，因此构建起来不合理。这项拟议的研究旨在提供一种协调的数学和计算机科学研究努力，以解决相互关联的软件问题集群，这些问题可能会削弱未来大型系统上的应用程序性能。在脉冲星项目下，PI使用各种经典和新颖的密集线性代数算法来探索众所周知的潜力，但现在很少使用脉动阵列设计原则来开发未来多核和异类系统的所有能力，构建到极大规模。如果能够创建一个软件平台，该平台可以对传统的脉动阵列体系结构进行虚拟化，允许其应用程序的粒度具有适当的灵活性，那么就可以产生使用这种数据驱动执行模型来在未来大规模并行和数据匮乏的HPC系统上实现卓越性能和可扩展性的库和应用程序。

More than seven years after traditional processor designs hit the edge of their power envelope, the path of extreme scale Computational Science to a 100 petaflop (Pflop/s) system, which researchers had hoped to be using by the middle of the coming decade, has never looked steeper. On current high performance computing (HPC) systems, the 'application-architecture performance gap,' i.e. the gap between theoretical peak performance and the performance realized by full applications is already substantial. But with clock frequencies now capped below 4 GHz and trending downward, latencies in key areas (e.g. memory access, bus, system interconnect) expected to remain relatively stagnant, and software parallelism required to increase by at least three orders of magnitude to make effective use of the tens of thousands of processors and millions of cores that 100 Pflop/s systems are projected to contain, it is now reasonable to worry that a widening application-architecture performance gap will make such systems unproductive to use and therefore irrational to build. The proposed research aims to provide the kind of coordinated math and computer science research effort needed to solve the interrelated cluster of software problems that threaten to cripple application performance on future large-scale systems. Under the PULSAR project, the PIs use a variety of both classic and novel dense linear algebra algorithms to explore the potential of well known, but now little used systolic array design principles to exploit all the power that future multi-core and heterogeneous systems, built to extreme scales. If a software platform that virtualizes classic systolic array architecture, allowing for suitable flexibility in the granularity of its application can be created, then libraries and applications that use this data-driven execution model to achieve outstanding performance and scalability on future massively parallel and data-starved HPC systems can be produced.