SHF: Small: Massively Parallel Server Processors

对在线服务不断增长的需求使数据中心面临着实现更高性能和提高能效的持续压力。然而，服务器CPU在十多年的时间里在性能和效率方面没有取得重大改进。值得注意的是，在同一时间段内，GPU在人工智能/机器学习（AI/ML）和高性能计算（HPC）领域的性能和能效方面都取得了突破性的改进。 AI/ML和HPC的这些巨大改进来自于采用单指令多线程（SIMT）组织的GPU。 这个项目旨在展示将SIMT组织应用于负责运行在线服务的服务器CPU的好处。现代服务器计算所花费的大部分能量不是在功能单元上，而是在负责获取、解码和调度指令和内存访问的外围设备上。SIMT组织将这些开销分摊到许多并发执行线程中。 这个项目利用了这样一个观察结果，即忙碌的高性能服务器经常并发地为类似甚至相同的请求提供服务，从而有机会跨服务器线程应用SIMT。 这项研究提供了一个详细的跨层研究的微架构和内存系统的发展，一个高性能的节能SIMT服务器架构。 该项目将在服务器系统环境中的SIMT微架构（分支预测、乱序执行、寄存器文件和其他核心参数）、存储器子系统（缓存和存储器层次结构、虚拟存储器、一致性、指令和数据预取）以及操作系统（向量系统调用和线程调度）方面产生创新。该团队计划在跨堆栈（架构，操作系统，嵌入式）研究工作中对学生进行广泛的实践培训。计划开发和发布公共基础设施，以探索服务器空间微架构研究。将开发的模拟器有可能成为处理器参数设计空间explorations.This奖项反映了NSF的法定使命的社区资源，并已被认为是值得通过使用基金会的智力价值和更广泛的影响审查标准进行评估的支持。

Ever-growing demand for online services places data centers under constant pressure to achieve higher performance and improved energy efficiency. However, server CPUs have not made significant improvements in performance and efficiency in more than a decade. Notably, during the same time frame, GPUs made breakthrough improvements in both performance and energy efficiency in the Artificial-Intelligence / Machine-Learning (AI/ML) and High-Performance-Computing (HPC) domains. These massive improvements in AI/ML and HPC come from GPUs embracing the Single-Instruction-Multiple-Threads (SIMT) organization. This project aims to demonstrate the benefits of applying the SIMT organization to the server CPUs responsible for running online services.The majority of the energy spent by modern server computing is not in the functional units, but in the peripherals responsible for fetching, decoding, and scheduling instructions and memory accesses. The SIMT organization amortizes these overheads across many concurrent threads of execution. This project leverages the observation that busy high-performance servers frequently service similar or even identical requests concurrently, leading to the opportunity of applying SIMT across server threads. This research offers a detailed cross-layer study of the microarchitecture and memory system toward the development of a high-performance energy-efficient SIMT server architecture. The project will yield innovations in SIMT microarchitecture (branch prediction, out-of-order execution, register files and other core parameters), memory subsystems (cache and memory hierarchy, virtual memory, coherence, instruction and data prefetch), and operating systems (vector system calls and thread scheduling) in the context of server systems. The team plans extensive hands-on training of students in cross-stack (Architecture, Operating System, Compilers) research work. Public infrastructure development and release for exploration of server-space micro-architecture studies are planned. The simulator that will be developed has the potential to become a community resource for processor parameter design space explorations.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.