SHF: Small: Addressing Challenges for the Next Decade of Massively Parallel NUMA Accelerators

SHF：小型：应对大规模并行 NUMA 加速器未来十年的挑战

• 批准号: 1910924
• 负责人: Timothy Rogers
• 金额: $ 49.54万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2023-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1910924&HistoricalAwards=false
• 关键词: SHF; Small; Addressing; Challenges; Next

The physical and economic principles that enabled Dennard scaling and Moore's law in the semiconductor industry have reached their breaking point. However, as the number of transistors economically fabricated on a single chip plateaus, the processor industry has pivoted to create single-package computing systems, composed of multiple sub-components known as chiplets. Chiplets, which communicate via high-bandwidth on-package networks, offer the potential for transparent performance scaling into the next decade. However, chiplets introduce challenging non-uniform memory access characteristics into single-package systems that have traditionally not been subject to these effects. This project develops techniques to overcome the challenges of non-uniform memory accesses on high-performance single- and multi-package systems without programmer intervention. Exploring programmer-transparent scaling mechanisms improves the portability and lifetime of programs, decreasing the cost and complexity of software. Through the creation of course content and undergraduate summer internships, the project fosters an understanding of how to program machines in a post-Moore world and how compute accelerators should be designed to minimize the impact on the end-programmer as system complexity increases.This project develops coordinated data placement and thread scheduling algorithms that leverage static information from the compiler and dynamic information from the runtime system to inform data placement and hardware-based thread scheduling. It advances the state-of-the-art by developing an open-source Graphic Processing Unit (GPU) simulator with a hierarchical interconnect that can be used to model both chiplet-based GPUs and multi-GPU systems. The researchers are exploring compiler informed data placement and thread scheduling in GPUs. Initial results demonstrate that a static analysis of the code can predict the data accessed by GPU threadblocks. Analysis shows that it is possible to determine which threads in a grid share memory pages, and the manner of that sharing, by building new static techniques that add an additional dimension to decades of work on compilers for sequential code. Using static information, in combination with runtime information provided by GPU drivers, the researchers are developing advanced data placement, prefetching, and thread scheduling algorithms. Both future chiplet-based designs and existing multi-GPU systems benefit from the development of these algorithms. Looking beyond the high-bandwidth memory used in GPUs today the project explores the system-level implications of heterogeneous memory in a chiplet-based system. Data placement and thread scheduling have even more importance in GPU systems of the future that make use of high bandwidth memory, traditional dynamic random-access memory, and non-volatile memory. The problem sizes in such systems are anticipated to be so large that opportunistic data placement and thread scheduling are even more critical than in conventional systems. The project uses sharing patterns based on the inter-kernel producer-consumer nature of machine learning workloads to change the program's code layout, runtime data placement, and threadblock scheduling algorithm to maximize locality in multi-node systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在半导体行业实现了丹纳德缩放和摩尔定律的物理和经济原则已经达到了他们的突破点。但是，随着在单个芯片高原上经济制造的晶体管数量，处理器行业已枢转创建单包计算系统，该系统由多个子组件组成，称为chiplets。通过高带宽的包装网络通信的Chiplet为未来十年的透明性能扩展提供了潜力。但是，奇普特（Chiplets）将具有挑战性的非均匀记忆访问特性引入了传统上不受这些影响的单包装系统。该项目开发了克服在没有程序员干预的情况下，在高性能单包系统和多包装系统上克服非均匀内存访问的挑战的技术。探索程序员 - 透明缩放机制可改善程序的可移植性和寿命，从而降低软件的成本和复杂性。通过创建课程内容和本科暑期实习，该项目促进了对如何在运动后世界中编程机器进行编程的理解调度。它通过开发具有层次互连的开源图形处理单元（GPU）模拟器来推进最新技术，该模拟器可用于模拟基于chiplet的GPU和多GPU系统。研究人员正在探索编译器知情的数据放置和GPU中的线程调度。初始结果表明，对代码的静态分析可以预测GPU ThreadBlocks访问的数据。分析表明，可以通过构建新的静态技术来确定网格共享内存页面中的哪些线程以及共享的方式，这些静态技术为连续代码的编译器上的数十年工作增加了一个额外的维度。使用静态信息，结合了GPU驱动程序提供的运行时信息，研究人员正在开发高级数据放置，预取程和线程调度算法。这些算法的开发都受益于未来的基于chiplet的设计和现有的多GPU系统。除了当今GPU中使用的高带宽内存之外，该项目还探索了基于chiplet的系统中异质内存的系统级含义。数据放置和线程调度在未来的GPU系统中更为重要，这些系统利用高带宽内存，传统的动态随机访问记忆和非挥发性内存。预计此类系统中的问题大小是如此之大，以至于机会性数据放置和线程调度比传统系统更为关键。该项目使用基于机器学习工作负载的内分内生产商 - 消费者的性质来改变程序的代码布局，运行时数据放置和ThreadBlock计划算法，以最大程度地提高多节点系统中的区域性。该奖项反映了NSF的法定任务，并通过评估范围的范围，该奖项反映了支持者的支持和宽广的知识群体。

项目成果

Mitigating GPU Core Partitioning Performance Effects

• DOI: 10.1109/hpca56546.2023.10070957
• 发表时间: 2023-02
• 期刊: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
• 作者: Aaron Barnes;Fangjia Shen;Timothy G. Rogers

SIMR: Single Instruction Multiple Request Processing for Energy-Efficient Data Center Microservices

SIMR：节能数据中心微服务的单指令多请求处理

• DOI: 10.1109/micro56248.2022.00040
• 发表时间: 2022
• 期刊: 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO
• 作者: Khairy, Mahmoud;Alawneh, Ahmad;Barnes, Aaron;Rogers, Timothy G.
• 通讯作者: Rogers, Timothy G.

Locality-Centric Data and Threadblock Management for Massive GPUs

• DOI: 10.1109/micro50266.2020.00086
• 发表时间: 2020-10
• 期刊: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: Mahmoud Khairy;Vadim Nikiforov;D. Nellans;Timothy G. Rogers

Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling

• DOI: 10.1109/isca45697.2020.00047
• 发表时间: 2018-10
• 期刊: 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
• 作者: Mahmoud Khairy;Zhesheng Shen;Tor M. Aamodt;Timothy G. Rogers

Deterministic Atomic Buffering

确定性原子缓冲

• DOI: 10.1109/micro50266.2020.00083
• 发表时间: 2020
• 期刊: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO
• 作者: Chou, Yuan Hsi;Ng, Christopher;Cattell, Shaylin;Intan, Jeremy;Sinclair, Matthew D.;Devietti, Joseph;Rogers, Timothy G.;Aamodt, Tor M.
• 通讯作者: Aamodt, Tor M.