SHF: Small: Collaborative Research: VLSI Design Predictability Improvement By New Statistical Techniques in Timing Analysis, Delay ATPG, and Optimization

SHF：小型：协作研究：通过时序分析、延迟 ATPG 和优化中的新统计技术提高 VLSI 设计可预测性

• 批准号: 1117975
• 负责人: Bao Liu
• 金额: $ 25万
• 依托单位: University of Texas at San Antonio
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1117975&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; VLSI

One of the most critical challenges in todays nanoscale VLSI design is the lack of predictability in analysis and optimization. As VLSI technology continues scaling in the nanometer domain, VLSI systems are subject to increasingly significant parametric variations coming from not only the manufacturing process but also the system runtime environment. Increasingly significant parametric variations lead to increasingly significant variations in IC timing performance, power consumption, and other product metrics. Existing VLSI statistical analysis techniques cannot accurately and efficiently capture such variations; this greatly compromises design optimization and design convergence, affecting product quality and time-to market. In this work the PIs plan to develop techniques for signal probability-based statistical timing analysis (SPSTA), which would achieve accurate performance estimates for different inputs, rather than input-oblivious pessimistic delay bounds. In this project, the PIs propose to build on the foundation of SPSTA to enable a new, predictive and less-pessimistic VLSI implementation methodology. Core techniques will span VLSI statistical analysis, delay test ATPG, and optimization techniques that exploit improved predictability. Specifically, there are three thrust areas in this project, and it is expected that that these techniques will outperform existing alternative techniques. The outcome of this project is critical to the cost-effective continuation of semiconductor technology scaling (i.e., Moore's Law), and to maintaining growth of the semiconductor industry's economic engine in the coming years. The broader impacts of the proposed project can be further measured by a strong education program including curriculum development and research training which incorporate statistical VLSI analysis and optimization techniques into the computer engineering programs at the PIs? institutions, and into course infrastructure that is broadly and openly available to others online. Following their established practices of well over a decade, the PIs will broadly disseminate their research results by publication, industry collaboration, and online posting of open-source software. This project will also allow the PIs to broaden participation of students from under-represented groups based on the minority institute status of UT San Antonio; it will help educational initiatives that are aimed at preparing the San Antonio regional economy to transform into a technology-oriented one.

当今纳米级 VLSI 设计中最关键的挑战之一是分析和优化缺乏可预测性。随着超大规模集成电路技术在纳米领域的不断扩展，超大规模集成电路系统受到越来越大的参数变化的影响，这些参数变化不仅来自制造过程，还来自系统运行时环境。越来越显着的参数变化会导致 IC 时序性能、功耗和其他产品指标发生越来越显着的变化。现有的VLSI统计分析技术无法准确有效地捕获此类变化；这极大地影响了设计优化和设计融合，影响了产品质量和上市时间。在这项工作中，PI 计划开发基于信号概率的统计时序分析 (SPSTA) 技术，该技术将实现对不同输入的准确性能估计，而不是忽略输入的悲观延迟界限。在该项目中，PI 建议在 SPSTA 的基础上构建一种新的、可预测的且不太悲观的 VLSI 实施方法。核心技术将涵盖 VLSI 统计分析、延迟测试 ATPG 以及利用改进的可预测性的优化技术。具体来说，该项目有三个重点领域，预计这些技术将优于现有的替代技术。该项目的成果对于半导体技术扩展（即摩尔定律）的成本效益持续以及维持未来几年半导体行业经济引擎的增长至关重要。拟议项目的更广泛影响可以通过强大的教育计划进一步衡量，包括课程开发和研究培训，将统计 VLSI 分析和优化技术纳入 PI 的计算机工程计划？机构，以及可供其他人在线广泛公开使用的课程基础设施。遵循十多年来的既定做法，PI 将通过出版、行业合作和在线发布开源软件来广泛传播他们的研究成果。该项目还将允许 PI 根据 UT 圣安东尼奥分校的少数族裔学院地位，扩大来自代表性不足群体的学生的参与；它将有助于旨在帮助圣安东尼奥地区经济转型为技术导向型经济的教育举措。