NEB: Scalable Perpendicular All-Spin Non-Volatile Logic Devices and Circuits with Hybrid Interconnection

NEB：具有混合互连的可扩展垂直全自旋非易失性逻辑器件和电路

• 批准号: 1124831
• 负责人: Jian-Ping Wang
• 金额: $ 130万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1124831&HistoricalAwards=false
• 关键词: NEB; Scalable; Perpendicular; Spin; Non

ABSTRACTIntellectual Merit: This project is awarded under the Nanoelectronics for 2020 and Beyond competition, with support by multiple Directorates and Divisions at the National Science Foundation as well as by the Nanoelectronics Research Initiative of the Semiconductor Research Corporation. The research will provide an alternative to CMOS technology based on an all-spin logic device. Although nanomagnetism plays a fundamental role in existing magnetic storage technologies, the implementation of processing has traditionally required the conversion of magnetic information (spin) to charge and then back to spin after the processing step is complete. This approach, however, realizes none of the advantages of working with pure spin currents, which promise much lower power dissipation and potentially greater scalability. An all-spin logic concept that has been inspired by a decade of progress in semiconductor and metallic spintronics would achieve all-spin operation, but only if substantial materials engineering, processing, and integration challenges can be overcome. An interdisciplinary team has been assembled that is uniquely positioned to address these challenges, which include (1) engineering of bits which can function as either magnetic tunnel junction spin injectors (for inputs) or giant magnetoresistance (GMR) sensors (for low impedance outputs), (2) integrating these bits with interconnecting channels fabricated from either normal metals, graphene or ZnO, (3) developing a process that will provide for isolation of the input and output stages of the bits while preserving the desirable spin transport properties of the interconnects, (4) a test protocol grounded in both spin transport physics and circuit design principles, and (5) a clear path for integration. The approach addresses one of the severe roadblocks to practical spintronics, which is the need for efficient spin transport across interfaces while meeting the simultaneous demands of an economic and fully scalable processing technology. The team consists of an expert on perpendicular magnetic anisotropy materials and spintronic device engineering (Wang), a spin-transport physicist (Crowell), a circuit design and fabrication engineer (Kim), a semiconductor materials and device engineer (Koester), and a semiconductor spintronic materials engineer (Ding, an international collaborator). Broader Impacts: The unique combination of materials engineering, device physics, process engineering, and circuit design in this program will lead to a new family of logic devices. Just as importantly, these four technical components will play a critical role in training the engineers and scientists who will be carrying out nanoelectronic research well beyond 2020. The team provides true interdisciplinary mentorship for graduate students in multiple departments. In addition to technical training in at least two disciplines, the PIs will emphasize student interaction with industrial partners and participation in activities that allow students to explain nanotechnology and spintronics to the public. The participants in this program will also interact continuously with an active community of researchers in magnetism, semiconductor device physics at the University of Minnesota and in the surrounding community. This will prepare the diverse group of project participants for careers spanning a continuum from basic research to the implementation of new technologies. Mentorship of younger students, including undergraduate researchers, is also a critical component of the program. The project will proactively recruit minorities, women, and under-represented groups as well as leverage existing university-wide efforts for promoting diversity and outreach.

摘要智力优势：该项目是在Nanoelectronics for 2020及以后的竞争中获得的，得到了国家科学基金会多个部门和部门以及半导体研究公司Nanoelectronics Research Initiative的支持。这项研究将为基于全自旋逻辑器件的CMOS技术提供一种替代方案。虽然纳米磁性在现有的磁存储技术中发挥着重要作用，但传统上，处理的实现需要将磁信息（自旋）转换为电荷，然后在处理步骤完成后再转换回自旋。然而，这种方法没有实现纯自旋电流工作的任何优点，纯自旋电流保证了低得多的功耗和潜在的更大的可扩展性。受到半导体和金属自旋电子学十年进展的启发，全自旋逻辑概念将实现全自旋操作，但前提是可以克服大量的材料工程，加工和集成挑战。一个跨学科的团队已经组装，是独特的定位，以解决这些挑战，其中包括（1）工程位，可以作为磁性隧道结自旋注入器，（用于输入）或巨磁阻（GMR）传感器（对于低阻抗输出），（2）将这些位与由普通金属、石墨烯或ZnO制造的互连通道集成，（3）开发将提供位的输入和输出级的隔离同时保持互连的期望自旋输运性质的工艺，（4）基于自旋输运物理和电路设计原理的测试协议，以及（5）用于集成的清晰路径。该方法解决了实际自旋电子学的严重障碍之一，即需要在满足经济和完全可扩展的处理技术的同时实现跨接口的高效自旋传输。该团队由垂直磁各向异性材料和自旋电子器件工程专家（Wang）、自旋输运物理学家（Crowell）、电路设计和制造工程师（Kim）、半导体材料和器件工程师（Koester）以及半导体自旋电子材料工程师（Ding，国际合作者）组成。更广泛的影响：材料工程，器件物理，工艺工程和电路设计的独特组合将导致一个新的逻辑器件系列。 同样重要的是，这四个技术组成部分将在培训工程师和科学家方面发挥关键作用，这些工程师和科学家将在2020年以后进行纳米电子研究。该团队为多个部门的研究生提供真正的跨学科指导。除了至少两个学科的技术培训外，PI还将强调学生与工业合作伙伴的互动，并参与允许学生向公众解释纳米技术和自旋电子学的活动。 该计划的参与者还将与明尼苏达大学和周围社区的磁性，半导体器件物理学研究人员的活跃社区不断互动。 这将为不同的项目参与者群体做好准备，使他们能够从事从基础研究到新技术实施的连续职业。 年轻学生的导师，包括本科研究人员，也是该计划的一个重要组成部分。该项目将积极招募少数民族，妇女和代表性不足的群体，并利用现有的大学范围内的努力，促进多样性和外展。