SHF: Large:Collaborative Research: Architecting the Next Generation Memory Hierarchy - A Holistic Approach
SHF: Large:Collaborative Research: Architecting the Next Generation Memory Hierarchy - A Holistic Approach
批准号:
1213052
负责人:
Chitaranjan Das
金额:
$136.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2012
资助国家:
美国
项目状态:
已结题
起止时间:
2012-08-01 至 2017-07-31
中文摘要
存储器系统仍然是几乎所有计算系统中的主要性能和功率瓶颈。而且,随着主要的应用程序、架构和技术趋势的发展,它也变得越来越重要。获取和处理实时数据的嵌入式应用程序、必须分析大型数据库的互联网和云应用程序以及需要处理大量数据集的exa-scale HPC应用程序只是需要高内存容量、性能和能效的数据密集型应用程序的几个例子。因此,在本发明中,众所周知的存储器墙问题已经变得更加难以克服,需要从根本上重新考虑未来计算平台的存储器层次结构设计。本提案的目标是从根本上全面地重新考虑整个存储器层次结构的设计,同时考虑新兴的设备/存储器技术,并利用系统堆栈的不同层--从设备到微处理器--的设计权衡。架构、编译器和运行时系统。该解决方案将涵盖架构和优化整个内存路径的创新,包括高速缓存,片上网络,内存控制器和主内存。目标是在未来十年内实现100倍的内存容量提升,同时提供5倍的性能提升和10倍的能效提升。这项研究有可能改变多核时代下一代存储系统的设计,这有望成为整个IT部门无处不在的一部分。这项研究的交叉性质可以在几个领域培育新的研究方向,跨越技术/能源感知设计,计算机体系结构,编译器和系统/应用软件。 随着内存系统成为几乎所有未来应用领域的支柱,这项研究的广泛影响可以加速未来应用程序的设计和部署。该项目将使研究成果转移到产业,加强本科生和研究生的培训,包括代表性不足的学生,并有助于开发新的研究和教学工具。
英文摘要
The memory system continues to be a major performance and powerbottleneck in nearly all computing systems. And, it is becomingincreasingly more so with major application, architecture, andtechnology trends. Embedded applications that acquire andprocess real-time data, Internet and cloud applications that have toanalyze large databases, and the exa-scale era HPC applications thatneed to crunch voluminous data sets are just a few examples ofincreasingly data-intensive applications that require high memorycapacity, performance, and energy efficiency. Thus, the well-known memory wall problem has become even more difficult to surmount andneeds a fundamental rethinking of the memory hierarchy design for futurecomputing platforms.The goal of this proposal is to fundamentally and holisticallyrethink the design of the entire memory hierarchy taking into considerationthe emerging device/memory technologies and to exploit the design trade-offsat different layers of the system stack -- from devices to micro-architecture,compilers and runtime systems. The solution will cover innovations inarchitecting and optimizing the entire memory path consisting of the caches,on-chip networks, memory controller and main memory. The objectiveis to enable 100X improvement in memory capacity over the nextdecade, while providing 5X improvement in performance and10X improvement in energy efficiency. The proposed research has the potential to transform the design ofnext-generation memory systems for the multi-core era, which is expectedto be a ubiquitous part of the entire IT sector.The cross-cutting nature of this research can foster new research directionsin several areas, spanning technology/energy-aware design, computer architecture,compilers, and system/application software. With the memory system formingthe backbone of nearly every envisioned future application domain, thebroader impact of this research can accelerate the design and deploymentof future applications. This project will enable transfer of researchresults to industry, enhance undergraduate and graduate student trainingincluding under-represented students, and contribute to the development of newresearch and teaching tools.
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