SHF: Medium: A Technology-Architecture-Algorithm Co-Design Exploration of Scalable Spiking Neural Networks (SNNs)

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Neuromorphic computing is an inspiring and ambitious problem because by understanding how the human nervous system is able to work efficiently using less than 20-Watts of power, we should be able to design intelligent computing systems that can solve complex problems like humans. While there have been significant advancements in the accuracy of artificial neural networks (ANNs), the quest for power efficiencies akin to biological systems remains elusive. Consequently, there has been significant interest in an approach called spiking neural networks (SNNs) which uses biologically-inspired event-driven spike communication. However, SNN design is still in its infancy, with need for exploring different neuromorphic computing models, learning algorithms, hardware substrates and designing a communication fabric that can scale to meet a strict power budget. This research seeks to explore the design space of scalable, low-power SNNs. The outcomes of this research could be highly valuable and will pave the way for an array of related research in designing intelligent machines. On the educational front, plans include the involvement of undergraduate and graduate students in this emerging research, where they will get exposure to cross-cutting topics in computer architecture, electronic devices, circuits, and applications. Female and minority students will be recruited to work in the project. Several Broadening Participation in Computing (BPC) activities such as summer camp for girls and collaboration with the Education Department to expose K-12 students to many areas of computer science will be pursued.The project seeks to take a comprehensive approach spanning device/circuit level innovations for designing extremely low-power spiking neurons and synapses, architectural level solutions for designing hierarchical communication networks, algorithm level optimizations to improve the accuracy of SNN models, and evaluation of the designs with different classes of applications. The proposed research consists of four research tasks. First, the team plans to investigate the design of neuron device primitives using Magnetic Tunnel Junction (MTJ)-based spintronic devices that are orders of magnitude more power efficient than existing technologies. Second, using these MTJ-based neuron tiles, the design space of a scalable on-chip interconnection fabric will be explored. Third, the research focuses on developing algorithmic solutions to enhance the accuracy of SNNs, and a hybrid solution to leverage the benefits of both SNNs and ANNs. Finally, the plan includes to develop a simulation platform to evaluate the performance and energy efficiency of different designs using diverse applications.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.