Reduced Basis Element Methods for Thermal Modeling of Integrated Circuits

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The objective of this project is to develop "Reduced Basis Element" techniques for thermal modeling of integrated circuits (ICs). Typical digital IC's are designed using standard cells from "technology libraries", such as NOT, NAND, NOR and XOR gates, flip-flops, adders, multipliers and coders/decoders, etc., each of which may consist of a number of semi-conductor transistors connected by metal interconnects. A normal IC will contain millions of these standard cells and as such it is computationally infeasible to perform detailed thermal simulations of an entire IC. However, the development of accurate and efficient thermal models is becoming increasingly important because of the increasing power density of computing systems. Furthermore, new technologies such as silicon-on-insulator (SOI) and 3D stacking only exacerbate chip-heating problems. The proposed work will capitalize on the geometric repetition inherent in an IC to develop accurate and computationally efficient thermal models. Techniques for dividing and classifying an IC's cells and interconnects into standard geometry blocks will developed. Compact reduced order models for these blocks will then be created and these models will be coupled together to predict the thermal behavior of an entire integrated circuit. The reduced order models will be based on proper orthogonal decomposition analysis of detailed simulation data of individual cells. As such, the reduced order models will not need any ad-hoc modeling assumptions. Coupling procedures will use approaches borrowed from discontinuous Galerkin finite element methods. The proposed approach will enable thermal simulations of an IC with accuracy comparable to that of a direct simulation at a computational cost which is affordable with today's computing machinery. Current computers pack more power into smaller packages than ever before, which often results in significant internal heating problems. Computer chip designers must make compromises based on the temperature distribution in the integrated circuits and need efficient and accurate thermal models to do this. Current models are derived using simplifying assumptions about the heat flows in the integrated circuit and do not provide detailed thermal data. These models limit designers from pursuing more advanced designs. This work aims to develop an efficient, high-fidelity tool that will enable more advanced designs to be tried while maintaining the short design cycle of the semiconductor industry. In addition, the basic framework that will be developed will be applicable to any problem having repeated geometric features such as stacked-cell batteries, solar cell panels, thermoelectric modules, etc. Thus, this technique could enable first-principles-based high-fidelity simulations in a wide range of fields. These simulations will in turn enable the next generation of advanced designs.