TWC: Phase: Medium: Collaborative Proposal: Understanding and Exploiting Parallelism in Deep Packet Inspection on Concurrent Architectures

TWC：阶段：中：协作提案：理解和利用并发架构深度数据包检查中的并行性

• 批准号: 1228782
• 负责人: Somesh Jha
• 金额: $ 95.08万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2018-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1228782&HistoricalAwards=false
• 关键词: TWC; Phase; Medium; Collaborative; Proposal

Deep packet inspection (DPI) is a crucial tool for protecting networks from emerging and sophisticated attacks. However, it is becoming increasingly difficult to implement DPI effectively due to the rising need for more complex analysis, combined with the relentless growth in the volume of network traffic that these systems must inspect. To address this challenge, future DPI technologies must exploit the power of emerging highly concurrent multi- and many-core platforms. Unfortunately, however, current DPI systems severely limit their use of parallelism by either resorting to coarse-grained load-balancing or restricting their analysis to very simple, hard-coded detectors.In order to fully exploit parallel hardware platforms, in this project we develop a comprehensive approach that introduces parallelism across all stages of the complex DPI pipeline. We investigate application-independent scheduling strategies that take existing DPI analyses and automatically parallelize their processing. We do so by mapping them into a domain-specific intermediary representation that abstracts from specifics of the underlying hardware architecture while providing low-level consistency guarantees. Conceptually, the project's goal is to virtualize and abstract parallelism as a fundamental primitive, just like how virtual memory abstracts away physical memory size limitations from programmers.

深度数据包检测（DPI）是保护网络免受新兴和复杂攻击的重要工具。然而，由于对更复杂分析的需求不断增加，再加上这些系统必须检查的网络流量不断增长，有效实施DPI变得越来越困难。 为了应对这一挑战，未来的DPI技术必须利用新兴的高并发多核和众核平台的强大功能。不幸的是，然而，目前的DPI系统严重限制了他们使用的并行性，无论是诉诸粗粒度的负载平衡或限制他们的分析，非常简单，硬编码detectors.To充分利用并行硬件平台，在这个项目中，我们开发了一个全面的方法，介绍了复杂的DPI管道的各个阶段的并行性。我们调查独立于应用程序的调度策略，采取现有的DPI分析和自动并行处理。我们这样做是通过将它们映射到一个特定于域的中介表示，抽象的底层硬件架构的细节，同时提供低级别的一致性保证。从概念上讲，该项目的目标是将并行性虚拟化和抽象化为一个基本要素，就像虚拟内存如何从程序员那里抽象出物理内存大小限制一样。