Collaborative Research: On-chip Multi-Channel Millimeter-wave Wireless Links for Multi-core Platforms

智能优势：根据摩尔-S定律，随着众所周知的不断扩大的趋势，传统的片上互连系统预计很快就会达到满足新兴多核处理器的性能需求和规格的能力非常有限的地步。根据国际半导体技术路线图(ITRS)，从长远来看，传统规模的材料创新将不再满足性能要求，需要新的互连范例。只有当底层片上通信链路能够以可接受的电源性能效率水平运行时，才能利用多核系统的计算能力。为了解决这一问题，提出了一种针对多核芯片的高带宽、远距离、多通道毫米波无线链路作为通信骨干的设计。该方案的研究目标将通过：(1)设计用于高吞吐量片上数据传输的片上、高效、单频和多频小型化天线；(2)设计能够实现多个非重叠、低功率、宽带无线链路的毫米波收发器；以及小世界无线片上网络(WiNoC)体系结构的性能评估。更广泛的影响：该提案涉及片上毫米波无线通信链路的设计，以支持大规模多核芯片的能效设计。多核处理平台已经出现，以满足许多重要应用的性能需求，如图形、金融和科学建模、生物监测、网络、多媒体和无线基础设施。这些不同的应用将受益于本文提出的低延迟、低功耗的片上通信基础设施。拟议的研究将通过允许本科生和研究生将课堂知识应用于研究问题来加强他们的教育。作为其Tera-Scale计算研究计划的一部分，英特尔正在积极推进可扩展多核架构的几个项目。因此，拟议的工作符合英特尔内部的一个重要重点领域。来自不同代表性不足群体的学生，包括妇女、非裔美国人和拉美裔美国人将参与这个项目。S项目的积极教育影响将与研究成果对整个社会产生的积极影响相辅相成。研究结果将广泛传播。除了在同行评议的期刊上发表外，结果还将在国际公认的会议上公布。

INTELLECTUAL MERIT: With the well-known trend of continued CMOS scaling, as per Moore?s Law, traditional on-chip interconnect systems are projected to soon reach the point of having a very limited ability to meet the performance needs and specifications of emerging many-core processors. According to the International Technology Roadmap for Semiconductors (ITRS), for the longer term, material innovation with traditional scaling will no longer satisfy performance requirements and new interconnect paradigms will be needed. The computing capabilities of many-core systems can be harnessed only if the underlying on-chip communication links can perform at an acceptable level of power performance efficiency. To address this problem, design of high-bandwidth, long-range and multi-channel millimeter (mm)-wave on-chip wireless links as communication backbones targeted for many-core chips is proposed. The research goals of this proposal will be achieved by: (1) Designing on-chip, highly efficient, single and multiband miniaturized antennas for high throughput on-chip data transfer; fabrication, testing and evaluation of prototype antennas including on-chip inkjet-printed antennas and (2) Designing mm-wave transceivers that enable multiple non-overlapping, low power, broadband wireless links and performance evaluation of small-world wireless Network-on-Chip (WiNoC) architectures. BROADER IMPACTS: This proposal addresses the design of on-chip mm-wave wireless communication links to support power efficient design of massive multi-core chips. Multi-core processing platforms have emerged to meet the performance needs of many important applications such as graphics, financial and scientific modeling, biomonitoring, networking, multimedia and wireless infrastructure. These diverse applications will benefit from the low latency, low power on-chip communication infrastructure proposed in this work. The proposed research will enhance the education of undergraduate and graduate students by allowing them to apply classroom knowledge to research problems. As part of its Tera-scale Computing Research Program, Intel is actively pursuing several projects on scalable multi-core architectures. Consequently, the proposed work aligns with an important thrust area within Intel. Students from various underrepresented groups, including women, African Americans and Hispanics will be engaged in this project. The project?s positive educational impacts will be complemented by the positive effect that the research outcomes are expected to have on society as a whole. Outcomes of the research will be broadly disseminated. In addition to publication in peer-reviewed journals, results will be presented at internationally recognized conferences.