Collaborative Research: On-chip Multi-Channel Millimeter-wave Wireless Links for Multi-core Platforms

智力优势：随着众所周知的趋势，继续CMOS规模，根据摩尔？s定律，传统的片上互连系统预计将很快达到具有非常有限的能力，以满足新兴的众核处理器的性能需求和规格的点。根据国际半导体技术路线图（ITRS），从长远来看，传统缩放的材料创新将不再满足性能要求，需要新的互连范式。只有当底层的片上通信链路能够以可接受的功率性能效率水平执行时，才能利用众核系统的计算能力。为了解决这个问题，设计高带宽，长距离和多通道毫米波（mm）的片上无线链路作为通信骨干为众核芯片的目标被提出。本计画的研究目标将透过以下几方面来达成：（1）设计高效能、单频与多频的小型化天线，以提供高通量的晶片上资料传输;包括芯片上喷墨印刷天线的原型天线的制造、测试和评估，以及（2）设计能够实现多个非重叠、低功率、宽带无线链路和小世界无线片上网络（WiNoC）架构的性能评估。更广泛的影响：该提案解决了片上毫米波无线通信链路的设计，以支持大规模多核芯片的节能设计。多核处理平台的出现是为了满足许多重要应用的性能需求，例如图形、金融和科学建模、生物监测、网络、多媒体和无线基础设施。这些不同的应用程序将受益于低延迟，低功耗的芯片上的通信基础设施，在这项工作中提出。拟议的研究将提高本科生和研究生的教育，让他们运用课堂知识的研究问题。作为其万亿级计算研究计划的一部分，英特尔正在积极开展多个可扩展多核架构项目。因此，拟议的工作与英特尔内部的一个重要的推动领域保持一致。来自各种代表性不足群体的学生，包括妇女、非洲裔美国人和西班牙裔美国人，将参与这一项目。项目？的积极教育影响将得到研究成果预期对整个社会产生的积极影响的补充。研究结果将广泛传播。除了在同行评审的期刊上发表外，研究结果还将在国际公认的会议上发表。

INTELLECTUAL MERIT: With the well-known trend of continued CMOS scaling, as per Moore?s Law, traditional on-chip interconnect systems are projected to soon reach the point of having a very limited ability to meet the performance needs and specifications of emerging many-core processors. According to the International Technology Roadmap for Semiconductors (ITRS), for the longer term, material innovation with traditional scaling will no longer satisfy performance requirements and new interconnect paradigms will be needed. The computing capabilities of many-core systems can be harnessed only if the underlying on-chip communication links can perform at an acceptable level of power performance efficiency. To address this problem, design of high-bandwidth, long-range and multi-channel millimeter (mm)-wave on-chip wireless links as communication backbones targeted for many-core chips is proposed. The research goals of this proposal will be achieved by: (1) Designing on-chip, highly efficient, single and multiband miniaturized antennas for high throughput on-chip data transfer; fabrication, testing and evaluation of prototype antennas including on-chip inkjet-printed antennas and (2) Designing mm-wave transceivers that enable multiple non-overlapping, low power, broadband wireless links and performance evaluation of small-world wireless Network-on-Chip (WiNoC) architectures. BROADER IMPACTS: This proposal addresses the design of on-chip mm-wave wireless communication links to support power efficient design of massive multi-core chips. Multi-core processing platforms have emerged to meet the performance needs of many important applications such as graphics, financial and scientific modeling, biomonitoring, networking, multimedia and wireless infrastructure. These diverse applications will benefit from the low latency, low power on-chip communication infrastructure proposed in this work. The proposed research will enhance the education of undergraduate and graduate students by allowing them to apply classroom knowledge to research problems. As part of its Tera-scale Computing Research Program, Intel is actively pursuing several projects on scalable multi-core architectures. Consequently, the proposed work aligns with an important thrust area within Intel. Students from various underrepresented groups, including women, African Americans and Hispanics will be engaged in this project. The project?s positive educational impacts will be complemented by the positive effect that the research outcomes are expected to have on society as a whole. Outcomes of the research will be broadly disseminated. In addition to publication in peer-reviewed journals, results will be presented at internationally recognized conferences.