CAREER: Scaling of Memristive Nanodevices and Arrays

本CAREER提案的研究目标是制造、测试、表征和理解具有前所未有的小特征尺寸和高封装密度的记忆性纳米器件和阵列。方法有：1)利用纳米压印、电子束刻蚀、嵌段共聚物定向自组装以及这些新一代纳米刻蚀技术的结合来缩放忆阻纳米器件；2)对不同长度尺度的器件/阵列进行了系统的电测量，并阐明了亚5nm尺度的缩放规律；3)不同长度尺度下的物理表征和器件物理研究。随着CMOS缩放接近极限，我们开发功能更多功能的新器件非常重要。忆阻器件是双端无源电子器件，使用高电阻和低电阻状态代替电荷存储为“1”和“0”。因此，设备的可扩展性不受量子效应的限制，而只取决于设备的尺寸。忆阻器件具有开关速度快、无擦除覆盖能力强、功耗低、耐用性强、数据保存时间长等特点。它们有望应用于非易失性存储器、非易失性逻辑、可重构电路和神经形态网络。该研究将在最密集的阵列（10 Tbits/in2）中产生更小的记忆纳米器件（3nm），为高密度非易失性数据存储和非易失性逻辑提供通用解决方案。随着不同尺寸的器件的出现，器件开关行为（功耗、耐用性、开关速度、数据保留时间等）作为尺寸函数的全谱研究将扩展到5nm以下。因此，拟议的研究将增加我们对开关机制/器件物理的理解，并将我们的知识扩展到尚未实现的物理体系。更广泛的影响拟议的工作将产生重大的科学、教育和社会影响。该研究将推进集成电路（IC）产业的变革性设备技术，维持美国在高科技领域的竞争力。这项职业计划的教育目标是培养下一代研究人员和工程师，并为学生、STEM（科学、技术、工程和数学）教师和公众创造激励学习的机会。实现这些目标的方法包括：1)为研究生和本科生设计创新的半导体和纳米技术课程；2)为本科生，特别是女性和少数民族学生提供鼓舞人心的研究经验；3)开展外展活动，如麻省大学阿默斯特分校面向K-12教师的纳米技术暑期学院，并在包括公众在内的更广泛的受众中推广利用艺术的纳米科学。

The research objectives of this CAREER proposal are to fabricate, test, characterize and understand memristive nanodevices and arrays with unprecedentedly small feature size and high packing density. The approaches are: 1) scaling of memristive nanodevices using nanoimprint lithograpy, electron beam lithography, directed self-assembly of block copolymer, and the combination of these next generation nanolithography technologies; 2) systematic electrical measurements of the devices/arrays of different length scale and elucidation of the scaling rules to sub-5 nm regime; and 3) physical characterization and underlying device physics studies at different length scales. Intellectual Merit As CMOS scaling approaches its limit, it is important that we develop new devices more versatile in functionality. Memristive devices are two-terminal passive electronic devices that use high and low resistance states instead of charge storage as '1's and '0's. As a result, the device scalability is not limited by the quantum effect but only dependent on how small the device one can make. Memristive devices have fast switch speed, overwrite ability without erase, low power consumption, high endurance and long data retention time. They are promising for applications in non-volatile memory, non-volatile logic, reconfigurable circuits and neuromorphic networks.This proposed research will lead to significantly smaller memristive nanodevices (3 nm) in the densest arrays (10 Tbits/in2), offering a universal solution to high-density non-volatile data storage and non-volatile logic. With devices of different dimensions available, full spectrum studies in device switching behavior (power consumption, endurance, switching speed, data retention time, etc.) as a function of size will be extended to sub-5 nm. Consequently, the proposed research will increase our understanding of the switching mechanisms/device physics and extend our knowledge to a physical regime not as yet achieved.Broader ImpactsThe proposed work will have significant scientific, educational and societal impact. The research will advance transformative device technologies for the integrated circuits (IC) industry, sustaining the U.S. competitiveness in high-technology areas. The education objectives of this CAREER proposal are to train next generation researchers and engineers, and to create motivating learning opportunities for students, STEM (Science, Technology, Engineering and Mathematics) teachers and the general public. The approaches to accomplishing these goals include: 1) innovative curricula design in semiconductors and nanotechnology for both graduate and undergraduate students; 2) inspiring research experience for undergraduate students, in particular women and minorities; and 3) engaging outreach activities such as Nanotechnology Summer Institute at UMass Amherst for K-12 teachers and promoting nanoscience using art among a much broader audience including the general public.