E2CDA: Type I: Collaborative Research: Energy-efficient analog computing with emerging memory devices

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The main goal of this project is to develop analog computing circuits that will greatly exceed their digital counterparts in energy-efficiency, speed, and density by employing emerging nonvolatile memory devices. Though analog circuits have been around for a long time, their applications in computing have been rather limited, largely due to the lack of efficient implementations of analog weights. This impediment could be overcome now due to the rapid progress in the emerging nonvolatile memory devices, such as metal-oxide memristors, which are the focus in this project. The analog memory functionality of memristors, combined with high retention and sub-10-nm scaling prospects, might for the first time enable extremely fast and energy-efficient analog implementations of many core operations, such as vector-by-matrix multiplication, which are central to many existing and emerging future applications such as internet-of-the-things and sensor networks, robotics, and energy efficient neuromorphic systems. The results of the proposed research will be integrated into educational curriculum and will help to train material science and electrical engineering students of all levels in this exciting field.The main caveat of the considered analog circuits is their limited operation accuracy, primarily due to the noise and variability in memory devices. The mitigation of this challenge by several means will be one of the main focuses of the project, and will be addressed with highly-interconnected research effort across device, circuit, and architectural layers. At the device level, detailed electrical characterization of analog operation and ways to improve it via material engineering, optimization of electrical stress, and development of efficient tuning algorithms to cope with device variations will be explored. Guided by experimentally-verified device models, the design of several representative analog computing circuits will be optimized. Circuit modeling tools will be developed to capture rich design trade offs in area, speed, energy efficiency, and precision, calibrated on experimental results from wafer-scale integrated memristor circuits, and used for detailed comparison with state-of-the-art digital counterparts. Finally, accurate circuit models will guide exploration of circuit architectures that mitigate limitations of analog computing and assist with detailed system level simulations.