SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies

功耗已成为跨所有平台扩展计算性能的根本障碍，从手持、嵌入式系统到笔记本电脑，再到服务器再到数据中心。缩小到亚纳米级的技术有助于每个芯片上晶体管的增长，这使得多核架构成为利用并行性和提高性能的一种高能效方法。只有当连接这些核心的底层片上网络(NoC)能够在芯片的功率预算内提供所需的带宽时，才能释放这些多核架构的计算能力。然而，使用传统的金属互连设计高能效、低延迟和高带宽的NoC，可以扩展到1000个内核或更多，这被证明是一个巨大的挑战。研究表明，光子学和无线等新兴技术有可能缓解未来NoC面临的关键带宽、功率和延迟挑战。然而，同时利用光子学和无线技术的混合NoC设计还没有被探索过。这项研究为彻底重新思考片上网络设计奠定了基础，并建议探索新兴互连技术的异构性，以设计性能可扩展和高能效的片上网络。我们的总体目标是将多种技术结合在一起，以实现我们具有挑战性的目标：(1)可扩展至1000个内核；(2)与最先进的金属互连相比，功率效率至少降低50%；(3)各种应用的高带宽和低延迟。首先，在体系结构一级，将为短距离(100个核心)部署光纤，以改善本地通信，并为远程通信部署无线，以便通过提供足够的全球带宽将核心数量扩大到1000个。其次，在电路层面，将探索混合收发信机架构，将基于SiGe/BiCMOS技术的新型超低功耗无线电路与光波导和环形谐振器集成在一起，以提供千核设计所需的大带宽。此外，将通过设计基于先进3D打印技术的毫米波/太赫兹频率宽带和定向天线来满足无线通信需求。该提案描述了一种结合技术、架构、算法和应用研究的变革性且可行的方法，用于设计可扩展且节能的NoC。这项研究的交叉性质将在几个领域培育新的研究方向，包括技术/能源感知NoC设计、新颖的计算机体系结构以及新兴技术的尖端建模和仿真工具。

Power dissipation has become a fundamental barrier to scaling computing performance across all platforms from handheld, embedded systems, to laptops, to servers to data centers. Technology scaling down to the sub-nanometer regime has aided the growth in transistors per chip that has made multi-core architectures a power-efficient approach to harnessing parallelism and improving performance. The computing capabilities of these multi-core architectures can be unleashed only if the underlying Network-on-Chip (NoC) connecting the cores can provide the required bandwidth within the power budget of the chip. However, the design of power-efficient, low-latency and high-bandwidth NoCs using traditional metallic interconnects that can scale to 1000 cores and beyond, is proving to be a significant challenge of enormous proportions. Research has shown that emerging technologies such as photonics and wireless have the potential to alleviate the critical bandwidth, power, and latency challenges of future NoCs. However, hybrid NoC designs taking advantages of both photonics and wireless technologies have not been explored. This research proposes to lay the groundwork for completely re-thinking the NoC design and proposes to explore heterogeneity of emerging interconnect technology for designing performance scalable, and power-efficient NoCs. The overall objective is to combine multiple technologies to achieve our challenging goals of (1) scalability to 1000 cores, (2) power efficiency of at least a 50% power reduction as compared to the state-of-the-art metallic interconnects, and (3) high bandwidth and low latency across a wide variety of applications. First, at the architecture level, optics will be deployed for short-range ( 100 cores) to improve local communication and wireless for long-range communication in order to scale the number of cores to 1000 by providing sufficient global bandwidth. Second, at the circuit level, hybrid transceiver architectures will be explored to integrate novel ultra-low power wireless circuits based on SiGe/BiCMOS technology with optical waveguides and ring-resonators to provide the large bandwidth desired for kilo-core designs. Furthermore, wireless communication requirements will be addressed by designing mm-wave/THz frequency broadband and directional antennas based on advanced 3D printing technology. This proposal describes a transformative and viable approach combining technology, architecture, algorithms and applications research for designing scalable and energy-efficient NoCs. The cross-cutting nature of this research will foster new research directions in several areas, spanning technology/energy-aware NoC design, novel computer architectures, and cutting-edge modeling and simulations tools for emerging technologies.