CSR: Small: A Time-Predictable Integrated CPU-GPU Architecture for Hard Real-Time Systems

CSR：小型：用于硬实时系统的时间可预测集成 CPU-GPU 架构

• 批准号: 1421577
• 负责人: Wei Zhang
• 金额: $ 50万
• 依托单位: Virginia Commonwealth University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-10-01 至 2019-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1421577&HistoricalAwards=false
• 关键词: CSR; Small; Time; Predictable; Integrated

Massive and energy-efficient computation capability, coupled with the enhanced programmability, makes Graphics Processing Units (GPUs) a desirable platform to accelerate a variety of data-intensive hard real-time applications such as medical data processing, autonomous auto navigation, and vision-based aircraft controls. The computer industry has already delivered several GPUs for embedded computing applications. However, none of these GPUs can guarantee time predictability, which is crucial for hard real-time systems. The integration of the CPU and the GPU on the same die makes it even more challenging to attain time predictability. The goal of this project is to fill this need, though investigation of the design of time-predictable integrated CPU-GPU architectures that can also offer high performance and energy efficiency.The project addresses this problem by: (i) systematic analysis and evaluation of time-unpredictability of GPUs and integrated CPU-GPUs; (ii) exploration of time-predictable and heterogeneous last-level cache (LLC) architectures for integrated CPU-GPUs, including private, partitioned, and locked LLCs; (iii) design of time-predictable and heterogeneous on-chip interconnection networks that can efficiently support communications within and across the CPUs and GPU; (iv) design of time-predictable memory controllers to enable scalable, safe, and tight WCET (Worst-Case Execution Time) estimation; (v) development of the first WCET analyzer for the proposed integrated CPU-GPU processor to support hard real-time computing. Other project activities include efforts to transition the results of the research to industry, integration of topics and projects related to the research in courses, and open-source distribution of software.

海量和高能效的计算能力，再加上增强的可编程性，使图形处理单元(GPU)成为加速各种数据密集型硬实时应用的理想平台，例如医疗数据处理、自主自动导航和基于视觉的飞机控制。计算机行业已经为嵌入式计算应用提供了几个GPU。然而，这些GPU都不能保证时间可预测性，这对硬实时系统至关重要。CPU和GPU在同一芯片上的集成使得实现时间可预测性变得更加具有挑战性。本项目的目标是通过对时间可预测的集成CPU-GPU体系结构的设计的研究来满足这一需求。该项目通过：(I)系统地分析和评估GPU和集成CPU-GPU的时间不可预测性；(Ii)探索用于集成CPU-GPU的时间可预测和异质的末级缓存(LLC)体系结构，包括私有、分区和锁定LC；(Iii)设计能够有效支持CPU和GPU内部和跨CPU和GPU之间通信的时间可预测的异质片上互连网络；(Iv)设计时间可预测的内存控制器，以实现可扩展、安全和紧凑的WCET(最坏情况执行时间)估计；(V)为拟议的集成CPU-GPU处理器开发第一个WCET分析器，以支持硬实时计算。其他项目活动包括努力将研究成果转化为产业，整合与课程研究有关的专题和项目，以及软件的开放源码分发。