SHF: Small: 100GHz DIgital Logic Using Cooled Commodity CMOS Technologies

SHF：小型：使用冷却商品 CMOS 技术的 100GHz 数字逻辑

• 批准号: 1422916
• 负责人: Kenneth Mai
• 金额: $ 45万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-07-15 至 2017-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1422916&HistoricalAwards=false
• 关键词: SHF; Small; 100GHz; DIgital; Logic

The scaling of integrated circuit process technology over the past few decades has enabled ever faster, smaller, and lower power micro-electronics. However, as process technologies near fundamental scaling limits, the pace of improvement in micro-electronics has slowed. This project seeks to boost the performance of digital integrated circuits made in current process technologies to unprecedented performance levels by cooling them to cryogenic temperatures. With this approximately order-of-magnitude performance gain, one may enable new classes of applications without needing fundamental breakthroughs in process technology. While much of the recent research in digital systems has been focused on exploiting parallelism (e.g., many-core CPUs), there remains a significant need for faster sequential processing. Even in highly parallelized systems, serial sections of code and Amdahl's Law can be bottlenecks to compute performance. Further, many users have critical, but un-modifiable, serial legacy code or applications that are inherently serial and non-parallelizable. The proposal explores extremely high clock rate digital systems in the "performance-at-all-costs" region of the design space using aggressively cooled commodity CMOS systems with a target clock rate of 100GHz, whereas the present commodity CMOS process technologies can achieve performance near 10GHz only. The project proposes to bridge this gap by building systems that use aggressive cooling, customized low-temperature circuits, and application specific architectures. Use of commodity CMOS process technologies enables both lower cost and higher integration densities than the more exotic processes, which heretofore were the only way to achieve the necessary digital logic and memory speed.

在过去的几十年中，集成电路工艺技术的规模化已经实现了更快、更小和更低功率的微电子器件。然而，随着工艺技术接近基本的缩放极限，微电子技术的改进步伐已经放缓。该项目旨在通过将数字集成电路冷却到低温温度，将当前工艺技术制造的数字集成电路的性能提升到前所未有的性能水平。有了这种近似数量级的性能增益，人们可以实现新的应用类别，而不需要在工艺技术上取得根本性突破。 虽然最近对数字系统的许多研究都集中在利用并行性（例如，众核CPU），仍然存在对更快的顺序处理的显著需求。即使在高度并行化的系统中，串行代码段和Amdahl定律也可能成为计算性能的瓶颈。此外，许多用户具有关键的但不可修改的串行遗留代码或固有地串行且不可并行的应用。该提案在设计空间的“不惜一切代价的性能”区域中探索极高时钟速率的数字系统，使用具有100GHz目标时钟速率的积极冷却的商品CMOS系统，而目前的商品CMOS工艺技术只能实现接近10GHz的性能。该项目建议通过构建使用积极冷却、定制低温电路和特定应用架构的系统来弥合这一差距。使用商品CMOS工艺技术能够实现比更奇特的工艺更低的成本和更高的集成密度，迄今为止，这是实现必要的数字逻辑和存储器速度的唯一方法。