TWC: Small: Accelerating Cryptographic Protocols with Reconfigurable Hardware

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This project is motivated by several observations. First, a number of cryptographic protocols have recently made the transition from pure theory to proof-of-concept instantiations. Second, in these instantiations, the remaining obstacles to genuine practicality seem amenable to hardware acceleration. An example is verifiable computation (one party is given assurance that another computed correctly); in this kind of protocol, computations are represented using a circuit formalism, and there are parallelizable cryptographic operations (modular exponentiation, etc.). Other protocols, including multi-party computation, functional encryption, etc., have analogous overheads.Given this motivation, the project explores the development, optimization, and application of hybrid software and hardware platforms for cryptographic protocols. The project is developing new techniques for parallelization on reconfigurable hardware, by drawing on integrated circuit design and testing methods; the project is also exploring hardware and software interfaces that enable efficient interaction between software and hardware accelerators. The methods include software and hardware design, implementation, modeling performance and costs, and rigorous experimental and empirical evaluation.Project results include a class of cryptographic protocols (verifiable computation, multi-party computation, functional encryption, etc.) suitable for practical use. The project's success thus makes a range of computing applications safer, including cloud computing and high assurance computing. Results are disseminated through peer-reviewed publications, and through code and experimental configurations released on a Web site. The project includes undergraduate involvement in research.