XPS: FULL: CCA: Collaborative Research: SPARTA: a Stream-based Processor And Run-Time Architecture

XPS：完整：CCA：协作研究：SPARTA：基于流的处理器和运行时架构

• 批准号: 1439097
• 负责人: Guang Gao
• 金额: $ 27.1万
• 依托单位: University of Delaware
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-08-01 至 2019-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1439097&HistoricalAwards=false
• 关键词: XPS; FULL; CCA; Collaborative; Research

Computer systems have undergone a fundamental transformation recently, from single‐core processors to devices with increasingly higher core counts within a single chip. The semi‐conductor industry now faces the infamous power and utilization walls, that is, physical constraints such as levels of power and energy consumption, but also reliability of the various components, must be taken into account not only during the chip fabrication process, but also when generating machine code and during program execution. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, and graphical processing units (GPUs) can eliminate the energy overheads of general‐purpose homogeneous cores. However, with future technological challenges pointing in the direction of on‐chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware. This project proposes to rethink the whole hardware‐software interface, by researching novel ways to design many‐core chip architectures and weaving heterogeneous components together and binding them by a fast and energy efficient on‐chip interconnection network. On top of it will lay a system software layer to efficiently drive applications and map them onto the best suited components of the chip. Both the hardware and software layer are encompassed by a novel execution model, which describes how to orchestrate the various parts of a program in the most efficient way (be it with respect to power and energy, performance, or reliability). To achieve these goals, the development of a new model of computation called SPARTA (Stream-based Processor And RunTime Architecture) is proposed. The proposed model combines a new runtime and compiler technology with a hierarchical heterogeneous many‐core chip and features hardware mechanisms for stream‐based fine‐grain program execution models to be reflected in different new software/hardware systems. Many issues are be envisioned, including programmability, scalability, performance evaluation, and power efficiency. Specifically, the goal is to identify the major challenges and obstacles toward an efficient exploitation of parallelism and scalability. To do so, traditional approaches will be re-evaluated by studying a collection of representative programs. A vertical design methodology is then proposed to effectively address the above challenges through the SPARTA approach and its implementation. In particular, the proposed cross-layer methodology consists of (a) a programming/execution model that will combine the Codelet model (leveraging our past research in dataflow models and extensions) with generalized streams: the Streaming Codelets, (b) an architecture model that will efficiently support the Streaming Codelets in heterogeneous hardware, and (c) a system software Stack that will be capable of effectively mapping Streaming Codelets to the proposed architecture. Finally, a qualitative and quantitative study of SPARTA will be performed via selected benchmarks and a consolidated methodology based on experimentation and analysis. The holistic cross-layer design methodology spanning the hardware/software stack and the reliability techniques developed from this research will significantly impact next generation multi‐core and System‐on‐Chip (SoC) architectures with improvements in energy efficiency, programmability, performance and robustness.

计算机系统最近经历了根本性的转变，从单核处理器到单芯片内具有越来越高核心数量的设备。半导体行业现在面临着臭名昭著的电力和利用壁垒，也就是说，不仅在芯片制造过程中，而且在生成机器代码和程序执行期间，都必须考虑物理限制，如电力和能源消耗水平，以及各种组件的可靠性。为了应对这些挑战，架构和技术层面的设计异构性将成为节能计算的主流方法，因为专用内核、加速器和图形处理单元(GPU)可以消除通用同质内核的能源开销。然而，随着未来的技术挑战指向片上芯片异构性的方向，以及由于并行编程的传统困难，产生能够利用异构性硬件的新的系统软件堆栈变得势在必行。该项目建议重新考虑整个硬件和软件接口，通过研究新的方法来设计许多核心芯片架构，将不同的组件编织在一起，并通过快速且节能的芯片互连网络将它们绑定在一起。在它的顶部将铺设一个系统软件层，以有效地驱动应用程序，并将它们映射到芯片的最合适的组件上。硬件层和软件层都包含在一个新的执行模型中，该模型描述了如何以最有效的方式(无论是关于功率和能量、性能还是可靠性)编排程序的各个部分。为了实现这些目标，提出了一种新的计算模型Sparta(Stream-Based Processor and Runtime Architecture)。提出的模型将新的运行时和编译器技术与分层的异构多核芯片相结合，并以基于流的细粒度程序执行模型的硬件机制为特征，以反映在不同的新软件/硬件系统中。可以预见许多问题，包括可编程性、可扩展性、性能评估和能效。具体地说，目标是确定有效利用并行性和可伸缩性的主要挑战和障碍。要做到这一点，将通过研究一系列有代表性的项目来重新评估传统方法。然后提出了一种垂直设计方法，以通过斯巴达方法及其实施有效地应对上述挑战。具体地说，所提出的跨层方法包括(A)将Codelet模型(利用我们过去在数据流模型和扩展方面的研究)与泛化的流：流Codelet相结合的编程/执行模型，(B)将在异类硬件中有效地支持流代码组的体系结构模型，以及(C)将能够有效地将流代码组映射到所提出的体系结构的系统软件堆栈。最后，将通过选定的基准和基于实验和分析的综合方法对斯巴达进行定性和定量研究。这项研究开发的跨越硬件/软件堆栈的整体跨层设计方法和可靠性技术将显著影响下一代多核和片上系统(SoC)架构，提高能效、可编程性、性能和健壮性。