XPS: FULL: CCA: Collaborative Research: SPARTA: a Stream-based Processor And Run-Time Architecture

最近，计算机系统经历了一场根本性的变革，从单一的计算机系统。核心处理器到在单个芯片内具有越来越高的核心数的设备。semi& # 8208;导体行业现在面临着臭名昭著的功率和利用墙壁，即物理限制，如功率和能耗水平，以及各种组件的可靠性，不仅在芯片制造过程中必须考虑，而且在生成机器码和程序执行期间也必须考虑。为了应对这些挑战，在架构和技术层面上设计的异构性将成为节能计算的主流方法，因为专用核心、加速器和图形处理单元（gpu）可以消除通用处理器的能源开销。目的均质芯。然而，随着未来的技术挑战指向的方向，由于芯片的异构性，以及传统的并行编程的困难，开发能够利用异构硬件的新系统软件栈变得势在必行。这个项目提出重新思考整个硬件&amp；#8208；软件接口，通过研究新方法设计许多&amp；#8208；核心芯片架构和编织异质组件在一起，并通过一个快速和节能的开关将它们绑定在一起&amp；#8208；芯片互连网络。在其上将铺设一个系统软件层，以有效地驱动应用程序，并将它们映射到最适合的芯片组件上。硬件层和软件层都包含在一个新的执行模型中，该模型描述了如何以最有效的方式编排程序的各个部分（无论是在电源和能源、性能还是可靠性方面）。为了实现这些目标，提出了一种新的计算模型，称为SPARTA（基于流的处理器和运行时体系结构）。该模型结合了一种新的运行时和编译器技术以及分层异构多系统。核心芯片和功能硬件机制流&amp；#8208；基于fine& # 8208;在不同的新软件/硬件系统中反映颗粒程序执行模型。可以预见许多问题，包括可编程性、可伸缩性、性能评估和电源效率。具体来说，目标是确定有效利用并行性和可伸缩性的主要挑战和障碍。为了做到这一点，传统的方法将通过研究一系列有代表性的项目来重新评估。然后提出了一种垂直设计方法，通过SPARTA方法及其实施有效地解决上述挑战。特别地，提出的跨层方法包括(a)一个编程/执行模型，它将Codelet模型（利用我们过去在数据流模型和扩展方面的研究）与通用流相结合：流代码集，(b)一个架构模型，它将有效地支持异构硬件中的流代码集，以及(c)一个系统软件堆栈，它将能够有效地将流代码集映射到提议的架构。最后，将通过选定的基准和以实验和分析为基础的综合方法对SPARTA进行定性和定量研究。跨越硬件/软件堆栈的整体跨层设计方法以及从本研究中开发的可靠性技术将对下一代多路集成电路产生重大影响。核心和系统&amp；#8208；芯片（SoC）架构与改进的能源效率，可编程性，性能和稳健性。

Computer systems have undergone a fundamental transformation recently, from single‐core processors to devices with increasingly higher core counts within a single chip. The semi‐conductor industry now faces the infamous power and utilization walls, that is, physical constraints such as levels of power and energy consumption, but also reliability of the various components, must be taken into account not only during the chip fabrication process, but also when generating machine code and during program execution. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, and graphical processing units (GPUs) can eliminate the energy overheads of general‐purpose homogeneous cores. However, with future technological challenges pointing in the direction of on‐chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware. This project proposes to rethink the whole hardware‐software interface, by researching novel ways to design many‐core chip architectures and weaving heterogeneous components together and binding them by a fast and energy efficient on‐chip interconnection network. On top of it will lay a system software layer to efficiently drive applications and map them onto the best suited components of the chip. Both the hardware and software layer are encompassed by a novel execution model, which describes how to orchestrate the various parts of a program in the most efficient way (be it with respect to power and energy, performance, or reliability). To achieve these goals, the development of a new model of computation called SPARTA (Stream-based Processor And RunTime Architecture) is proposed. The proposed model combines a new runtime and compiler technology with a hierarchical heterogeneous many‐core chip and features hardware mechanisms for stream‐based fine‐grain program execution models to be reflected in different new software/hardware systems. Many issues are be envisioned, including programmability, scalability, performance evaluation, and power efficiency. Specifically, the goal is to identify the major challenges and obstacles toward an efficient exploitation of parallelism and scalability. To do so, traditional approaches will be re-evaluated by studying a collection of representative programs. A vertical design methodology is then proposed to effectively address the above challenges through the SPARTA approach and its implementation. In particular, the proposed cross-layer methodology consists of (a) a programming/execution model that will combine the Codelet model (leveraging our past research in dataflow models and extensions) with generalized streams: the Streaming Codelets, (b) an architecture model that will efficiently support the Streaming Codelets in heterogeneous hardware, and (c) a system software Stack that will be capable of effectively mapping Streaming Codelets to the proposed architecture. Finally, a qualitative and quantitative study of SPARTA will be performed via selected benchmarks and a consolidated methodology based on experimentation and analysis. The holistic cross-layer design methodology spanning the hardware/software stack and the reliability techniques developed from this research will significantly impact next generation multi‐core and System‐on‐Chip (SoC) architectures with improvements in energy efficiency, programmability, performance and robustness.