SHF: Small: Collaborative Research: Multi-level Non-volatile FPGA Synthesis to Empower Efficient Self-adaptive System Implementations

SHF：小型：协作研究：多级非易失性 FPGA 综合，实现高效自适应系统

• 批准号: 1527464
• 负责人: Chengmo Yang
• 金额: $ 25万
• 依托单位: University of Delaware
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2019-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1527464&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Multi

Self-adaptivity is a key requirement for many electronic devices to consistently interact with the dynamic, uncertain, and noisy physical environment. While Field Programmable Gate Arrays (FPGAs), being reconfigurable, are a natural platform for implementing such devices, it is becoming more and more difficult for traditional FPGAs to keep up with the ever-increasing scale and complexity of self-adaptive applications due to the limited scalability, high leakage power, and severe process variations of CMOS technologies. A set of prior research projects demonstrated that it is technically feasible to construct FPGAs based on non-volatile memories (NVMs). These NV-FPGAs offer attractive features such as better scalability, superior energy efficiency, near-zero power-on delay, anti-radiation, as well as the ability to store more than one bit per cell. However, NV-FPGAs also display a complex design space involving information density, read and write speeds, data retention time, and device endurance. When used for self-adaptive systems, the distinctive NVM characteristics may influence reconfiguration speed, clock frequency, circuit functionality, memory performance, and/or device lifetime.This project addresses this technology gap as it prepares NV-FPGAs for more demanding self-adaptive systems. This project aims to fine-tune various procedures on the FPGA synthesis flow based on NVM characteristics, so as to exploit their advantages and mitigate their shortcomings. First, considering the needs of self-adaptive applications, this project fine-tunes various steps on the FPGA synthesis flow. Novel techniques are proposed to optimize task scheduling, data allocation, logic mapping, placement, and routing to improve reconfiguration speed, energy efficiency, reliability, and endurance of NVM FPGAs. Second, this project explores the rich NVM design space and sets different optimization goals for look-up tables, flip-flops, and on-chip memories. The success of this project will lead to a long-lasting, rapid-adaptive, reliable, and energy-efficient platform better suited to the needs of a wide range of applications with self-adaptivity requirement, including healthcare, wellness, industry, and even military applications, all of which are critical for the United States to drive its new strategies of innovation and technology. It will also train a diverse type of engineers to design the future generation of embedded and cyber-physical systems with the cutting-edge technology of non-volatile memories. Algorithms and tools developed in this project will be made publicly available so that they will benefit the entire scientific community.

自适应是许多电子设备与动态、不确定和嘈杂的物理环境持续交互的关键要求。虽然现场可编程门阵列（fpga）具有可重构性，是实现此类器件的天然平台，但由于CMOS技术的可扩展性有限、高泄漏功率和严重的工艺变化，传统fpga越来越难以跟上不断增长的自适应应用规模和复杂性。一系列先前的研究项目表明，基于非易失性存储器（NVMs）构建fpga在技术上是可行的。这些nv - fpga具有更好的可扩展性、卓越的能效、接近于零的上电延迟、抗辐射以及每个单元存储超过1位的能力等吸引人的特性。然而，nv - fpga也显示出复杂的设计空间，涉及信息密度、读写速度、数据保留时间和设备耐用性。当用于自适应系统时，独特的NVM特性可能会影响重构速度、时钟频率、电路功能、内存性能和/或设备寿命。该项目解决了这一技术差距，因为它为要求更高的自适应系统准备了nv - fpga。本项目旨在基于NVM特性对FPGA合成流程上的各种程序进行微调，以挖掘其优点，减轻其缺点。首先，考虑到自适应应用的需要，本项目对FPGA合成流程的各个步骤进行了微调。提出了优化任务调度、数据分配、逻辑映射、布局和路由的新技术，以提高NVM fpga的重构速度、能效、可靠性和耐用性。其次，本项目探索了丰富的NVM设计空间，并为查找表、触发器和片上存储器设定了不同的优化目标。该项目的成功将导致一个持久，快速适应，可靠和节能的平台，更好地适应具有自适应要求的广泛应用的需求，包括医疗保健，健康，工业甚至军事应用，所有这些都对美国推动其创新和技术的新战略至关重要。它还将培养不同类型的工程师，设计下一代嵌入式和网络物理系统，采用尖端的非易失性存储器技术。在这个项目中开发的算法和工具将向公众开放，以便使整个科学界受益。