SHF: Small: Collaborative Research: Multi-level Non-volatile FPGA Synthesis to Empower Efficient Self-adaptive System Implementations

SHF：小型：协作研究：多级非易失性 FPGA 综合，实现高效自适应系统

• 批准号: 1527506
• 负责人: Jingtong Hu
• 金额: $ 25万
• 依托单位: Oklahoma State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2018-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1527506&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Multi

Self-adaptivity is a key requirement for many electronic devices to consistently interact with the dynamic, uncertain, and noisy physical environment. While Field Programmable Gate Arrays (FPGAs), being reconfigurable, are a natural platform for implementing such devices, it is becoming more and more difficult for traditional FPGAs to keep up with the ever-increasing scale and complexity of self-adaptive applications due to the limited scalability, high leakage power, and severe process variations of CMOS technologies. A set of prior research projects demonstrated that it is technically feasible to construct FPGAs based on non-volatile memories (NVMs). These NV-FPGAs offer attractive features such as better scalability, superior energy efficiency, near-zero power-on delay, anti-radiation, as well as the ability to store more than one bit per cell. However, NV-FPGAs also display a complex design space involving information density, read and write speeds, data retention time, and device endurance. When used for self-adaptive systems, the distinctive NVM characteristics may influence reconfiguration speed, clock frequency, circuit functionality, memory performance, and/or device lifetime.This project addresses this technology gap as it prepares NV-FPGAs for more demanding self-adaptive systems. This project aims to fine-tune various procedures on the FPGA synthesis flow based on NVM characteristics, so as to exploit their advantages and mitigate their shortcomings. First, considering the needs of self-adaptive applications, this project fine-tunes various steps on the FPGA synthesis flow. Novel techniques are proposed to optimize task scheduling, data allocation, logic mapping, placement, and routing to improve reconfiguration speed, energy efficiency, reliability, and endurance of NVM FPGAs. Second, this project explores the rich NVM design space and sets different optimization goals for look-up tables, flip-flops, and on-chip memories. The success of this project will lead to a long-lasting, rapid-adaptive, reliable, and energy-efficient platform better suited to the needs of a wide range of applications with self-adaptivity requirement, including healthcare, wellness, industry, and even military applications, all of which are critical for the United States to drive its new strategies of innovation and technology. It will also train a diverse type of engineers to design the future generation of embedded and cyber-physical systems with the cutting-edge technology of non-volatile memories. Algorithms and tools developed in this project will be made publicly available so that they will benefit the entire scientific community.

自适应性是许多电子设备与动态，不确定和嘈杂的物理环境一致相互作用的关键要求。尽管可重构的现场可编程栅极阵列（FPGA）是实现此类设备的自然平台，但由于有限的可伸缩性，高泄漏功率和CMOS技术的严重过程，传统FPGA对传统FPGA的越来越难以跟上自动适应应用的不断增强的规模和复杂性。一组先前的研究项目表明，基于非易失性记忆（NVM）构建FPGA在技术上是可行的。这些NV-FPGA提供了吸引人的功能，例如更好的可伸缩性，较高的能效率，接近零的电动延迟，抗辐射以及每个单元格储存多个位以上的能力。但是，NV-FPGA还显示一个复杂的设计空间，涉及信息密度，读写速度，数据保留时间和设备耐力。当用于自适应系统时，独特的NVM特性可能会影响重新配置速度，时钟频率，电路功能，内存性能和/或设备寿命。该项目在为NV-FPGA准备更高苛刻的自适应系统时解决此技术差距。该项目旨在根据NVM特征微调有关FPGA合成流的各种程序，以利用其优势并减轻其缺点。首先，考虑到自适应应用的需求，该项目对FPGA合成流进行微调。提出了新的技术来优化任务调度，数据分配，逻辑映射，放置和路由，以提高NVM FPGA的重新配置速度，能效，可靠性和耐力。其次，该项目探索了丰富的NVM设计空间，并为查找表，触发器和片上记忆设定了不同的优化目标。该项目的成功将导致持久，快速自适应，可靠和节能的平台，更适合具有自适应要求的广泛应用需求，包括医疗保健，健康，工业，工业甚至军事应用，所有这些应用程序对于美国推动其新的创新和技术策略至关重要。它还将培训各种类型的工程师，以使用非易失性记忆的最先进技术设计未来的嵌入式和网络物理系统。该项目中开发的算法和工具将公开使用，以使它们受益于整个科学界。