SHF: Small: Locality-Aware Concurrency Platforms

标题：shf：Small：Locality-Aware并发平台现代计算机具有复杂的内存层次结构，其中包括必须有效利用以获得性能的多个级别的“缓存”。如果一个程序的执行可以有效地利用底层的高速缓冲存储器层次结构，那么它就被称为具有良好的局部性或高速缓存效率。由于处理器的速度增长快于内存访问延迟，因此优化程序的局部性往往比最小化在处理器上执行的指令数量更重要。随着“多核”系统的流行，针对局部性的优化变得更加关键，因为处理器上核心数量的增加会对每个核心可用的内存带宽和容量造成压力。然而，为现有的多核计算机编写有效利用高速缓存层次结构的并行程序是一项挑战。该项目旨在开发一个并行编程平台，使程序员能够在不担心局部性的情况下编写并行机程序，并且该平台以缓存高效的方式转换和执行程序。在智力优势方面，这项研究将促进对调度算法、编译器转换和运行时自动化的理解。该项目更广泛的重要性在于，程序员将能够为多核系统编写可移植、高性能和高速缓存高效的程序，同时与编写高速缓存高效代码的传统方法相比，显著减少编程工作量。该项目产生的平台将在万维网上免费提供，这可以实现高效的软件。编写高速缓存高效的并行程序是具有挑战性的，因为并行程序中的局部性是算法设计、调度和底层机器配置的函数，并且这些因素往往是紧密耦合的。此外，在并行平台上，性能取决于负载平衡和缓存效率，而这往往是相互竞争的目标。为了设计一个位置感知的并行编程平台，该项目将采取综合方法，将调度理论、算法设计、运行时系统支持和编译器转换方面的努力结合起来。在调度理论领域，PI将系统地研究负载平衡和缓存效率之间的权衡，并设计为两者提供合理保证的调度器。由于高速缓存效率还取决于程序本身，PI将研究高速缓存高效算法的设计模式，并利用这一经验来调查一组程序转换，以将普通程序转换为能够以高速缓存高效的方式执行的程序。这些见解将在一个由编译器和运行时系统组成的原型并发平台中实现，以便研究有效的机制来支持为以高速缓存高效的方式调度并行程序而开发的可证明是好的策略。

Title: SHF: Small: Locality-Aware Concurrency PlatformsModern machines have complex memory hierarchies consisting of many levels of "cache" that must be utilized effectively to gain performance. A program is said to have good locality or cache efficiency if its execution can utilize the underlying cache memory hierarchy effectively. Since the speed of processors is growing faster than the memory access latency, it is often more important to optimize one's program for locality than to minimize the number of instructions executed on the processor. With the prevalence of "multicore" systems, optimizing for locality becomes even more critical, since increase in the number of cores on a processor puts pressure on both the memory bandwidth and capacity available for each core. Writing parallel programs that utilize the cache hierarchy effectively for existing multicore machines is challenging, however. This project aims to develop a parallel programming platform that enables the programmer to program a parallel machine without worrying about locality, and the platform transforms and executes the program in a cache-efficient way. In terms of intellectual merits, this research will advance the understanding of scheduling algorithms, compiler transformations, and runtime automation. The project's broader importance is that programmers will be able to write portable, high-performant and cache-efficient programs for multicore systems while significantly reducing the programming effort compared to the traditional approach in writing cache-efficient code. The platform produced by this project will be made freely available on the World Wide Web, which can enable highly-efficient software.Writing cache-efficient parallel programs is challenging, because locality in a parallel program is a function of algorithm design, scheduling, and underlying machine configuration, and these factors are often tightly coupled. In addition, on parallel platforms, the performance depends on both load-balancing and cache efficiency, and these are often competing objectives. To design a locality-aware parallel programming platform, the project will take an integrated approach that combines efforts in scheduling theory, algorithmic design, runtime system support, and compiler transformations. In the realm of scheduling theory, the PIs will systematically study the trade-offs between load-balancing and cache efficiency, and design schedulers that provide sensible guarantees for both. Since cache-efficiency also depends on the program itself, the PIs will study the design patterns of cache-efficient algorithms and draw on this experience to investigate a set of program transformations to convert an ordinary program into one that can be executed in a cache efficient manner. These insights will be implemented in a prototype concurrency platform consisting of a compiler and a runtime system in order to study efficient mechanisms to support provably good policies developed for scheduling parallel programs in a cache-efficient manner.