NeTS: Small: Addressing End-system Bottlenecks in High-speed Networks

NeTS：小型：解决高速网络中的终端系统瓶颈

• 批准号: 1528087
• 负责人: Dipak Ghosal
• 金额: $ 50万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-10-01 至 2019-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1528087&HistoricalAwards=false
• 关键词: NeTS; Small; Addressing; End; system

The rate at which a single processor in a computer can execute instructions has not changed much in years, and major technological breakthroughs will be required to double the current best rates. On the other hand, the rate at which the network can deliver data is increasing rapidly and is expected to grow by an order of magnitude in the next few years. Because of the widening gap between the rate at which the network can deliver data and the rate at which a processor can process the data, it is becoming increasingly difficult for a single processor to keep up using current protocols and computer architectures. Computer architects have compensated for the fact that processor speeds are no longer increasing by putting multiple processor cores on each die, and while these multicore systems have high aggregate processing capacities, attaining predictable performance for the commonly adopted communication protocols requires complex manual tuning. In prior work, the concept of affinity (intelligently binding processes to processors) was leveraged to exploit the hardware parallelism of current and next generation computers. This project will build upon this prior expertise and leverage statistical and control theoretic methods to manage end-to-end performance of high-speed flows. The process of careful characterization of current technology, followed by analysis, and finally middleware tool development will affords the maximum impact on shaping best practices while minimizing any impact on distributed application development processes.This project will characterize the end-system bottlenecks that arise during data transfers required in different distributed scientific and business applications. What is learnt will drive the development of introspective end-system aware models, which will allow the auto-tuning of data transfers. This tuning will consider both latency and throughput requirements of the applications. Flow striping methods that exploit multicore end-systems and adapt to the end-system bottlenecks will be developed. This will require addressing many new issues, such as assigning flows to cores while taking into account various (application, cache, and interrupt) affinities. Additionally, the underlying topology of the cache (inclusive vs. exclusive), the memory organization, and the heterogeneity of the cores will be considered when controlling the end-to-end flows. Memory-mapped network channels, such as Remote Direct Memory Access over Converged Ethernet will be investigated, for data transfers over wide-area networks. Towards this end, memory management, message synchronization and end-to-end flow control to enable remote messaging for different types of network flows will be designed, implemented and evaluated. From the end-system architectural perspective, cache architectures that can significantly improve the network I/O performance will be proposed and investigated.Broader Impacts: This project, which lies at the intersection of computer networks, computer systems, operating systems, and distributed applications, will provide a platform to train graduate students in both analytical and experimental methods. Senior Design projects for undergraduates will be defined that will be closely related to the project and involve profiling distributed applications in high-speed network testbeds. Industry partnerships will be established to design new protocols and optimize the performance of distributed applications, as well as contribute to the design of next generation networked computer system.

计算机中的单个处理器执行指令的速度多年来没有太大变化，需要重大技术突破才能将目前的最佳速度提高一倍。另一方面，网络可以传输数据的速率正在快速增长，预计在未来几年内将以一个数量级的速度增长。由于网络传输数据的速率和处理器处理数据的速率之间的差距越来越大，单个处理器越来越难以跟上当前的协议和计算机架构。 计算机架构师已经通过在每个芯片上放置多个处理器内核来补偿处理器速度不再增加的事实，并且虽然这些多核系统具有高聚合处理能力，但是为通常采用的通信协议获得可预测的性能需要复杂的手动调整。 在以前的工作中，亲和性（智能绑定进程到处理器）的概念被用来利用当前和下一代计算机的硬件并行性。 该项目将建立在这一先前的专业知识，并利用统计和控制理论的方法来管理高速流的端到端性能。仔细描述当前技术的过程，然后进行分析，最后中间件工具的开发将提供最大的影响，塑造最佳实践，同时尽量减少对分布式应用程序开发过程的影响。本项目将描述在不同的分布式科学和商业应用程序中所需的数据传输过程中出现的终端系统瓶颈。所学到的将推动内省的终端系统感知模型的发展，这将允许数据传输的自动调整。此调优将考虑应用程序的延迟和吞吐量要求。将开发利用多核终端系统并适应终端系统瓶颈的流条带化方法。这将需要解决许多新问题，例如在考虑各种（应用程序，缓存和中断）亲和性的同时将流分配给核心。此外，在控制端到端流时，将考虑该高速缓存的底层拓扑（包含与排他）、内存组织和内核的异构性。 存储器映射的网络通道，如融合以太网远程直接存储器访问将被调查，在广域网上的数据传输。为此，将设计、实施和评估内存管理、消息同步和端到端流量控制，以便为不同类型的网络流量提供远程消息。从终端系统架构的角度来看，缓存架构，可以显着提高网络I/O performance将被提出和investigated.Broader影响：这个项目，它位于计算机网络，计算机系统，操作系统和分布式应用程序的交叉点，将提供一个平台，培养研究生在分析和实验方法。本科生的高级设计项目将被定义为与项目密切相关，并涉及在高速网络测试平台中分析分布式应用程序。 将建立行业合作伙伴关系，以设计新的协议和优化分布式应用程序的性能，并为下一代网络计算机系统的设计做出贡献。