SHF: Small: Development of Integrated Memristive Crossbar Circuits for Pattern Classification Applications

SHF：小型：用于模式分类应用的集成忆阻交叉电路的开发

• 批准号: 1528205
• 负责人: Dmitri Strukov
• 金额: $ 45万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-07-15 至 2018-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1528205&HistoricalAwards=false
• 关键词: SHF; Small; Development; Integrated; Memristive

Building artificial neural networks capable of matching the performance and functionality of their biological counterparts is one of the grand challenges in computing. The broad goal of this research project is to address one important aspect of this grand challenge, e.g., creating efficient hardware for implementing artificial neural networks. Artificial neural network based information processing, suitable for low precision applications, may indeed be particularly important in the present day context of energy efficient computing. If successful, this research has the potential to have broad and long lasting societal impact by improving energy efficiency and enriching functionality of existing electronics, and creating a large number of novel applications. The project will involve graduate and undergraduate students, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.The high complexity, connectivity and parallelism of neural networks make conventional technology hardware implementations rather inefficient. The core idea of this project is to utilize emerging memory devices, specifically memristors, which are essentially super-dense analog nonvolatile memory devices, to implement compact and energy efficient artificial neural networks. A particular experimental focus of the project is on demonstration of a hybrid memristive crossbar circuit implementation of small-scale (hundreds of neurons, thousands of synapses) multilayer perceptron performing pattern classification task. Although such a demonstration may only have a rather simple functionality, the resulting classifier would have all the key features of state-of-the-art deep learning convolutional neural network classifiers. The major focus is on the development of training algorithms compatible with memristor switching kinetics and investigation of the tradeoffs between complexity of hybrid circuits and classification performance. Theoretical modeling will guide experimental work towards most efficient implementations as well as ensure scaling of the approach to perform practical applications. Resolving hardware challenges for relatively simple neural networks would be essential for the development of more advanced neural networks capable of performing complex cognitive tasks.

构建能够与生物神经网络的性能和功能相匹配的人工神经网络是计算领域的重大挑战之一。这项研究项目的广泛目标是解决这一重大挑战的一个重要方面，例如，为实现人工神经网络创造高效的硬件。基于人工神经网络的信息处理适用于低精度应用，在当今能源效率计算的背景下可能确实特别重要。如果成功，这项研究有可能通过提高能源效率和丰富现有电子产品的功能，并创造大量新的应用，产生广泛和持久的社会影响。该项目将涉及研究生和本科生，包括代表性不足的群体的成员，因此将有助于扩大信息和通信技术领域的劳动力。神经网络的高度复杂性、连通性和并行性使得传统技术的硬件实施效率相当低。该项目的核心思想是利用新兴的存储器件，特别是忆阻器，本质上是超高密度的模拟非易失性存储器件，来实现紧凑和节能的人工神经网络。该项目的一个特别的实验重点是演示一个混合记忆交叉开关电路实现的小规模(数百个神经元，数千个突触)多层感知器执行模式分类任务。尽管这样的演示可能只具有相当简单的功能，但得到的分类器将具有最先进的深度学习卷积神经网络分类器的所有关键特征。主要的重点是开发与忆阻器开关动力学兼容的训练算法，以及研究混合电路的复杂性和分类性能之间的权衡。理论建模将指导实验工作，以实现最有效的实施，并确保该方法的规模，以执行实际应用。解决相对简单的神经网络的硬件挑战，对于开发能够执行复杂认知任务的更先进的神经网络至关重要。