SHF: Small: Design, Modeling and Automation of Monolithically Stackable Hybrid CMOS/Memristor Programmable Circuits

SHF：小型：单片堆叠混合 CMOS/忆阻器可编程电路的设计、建模和自动化

• 批准号: 1017579
• 负责人: Dmitri Strukov
• 金额: $ 48.99万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1017579&HistoricalAwards=false
• 关键词: SHF; Small; Design; Modeling; Automation

Field Programmable Gate Arrays (FPGAs) become increasingly attractive alternatives to conventional microprocessors and application specific integrated circuits. Indeed, FPGAs combine the best properties of both, such as highly customized datapath and cost efficiency, while with miniaturization of complementary metal oxide semiconductor (CMOS) technology during past decades the capacity of FPGAs is now close to a million programmable logic blocks. This opens new opportunities for the use of FPGAs, in particular, in signal, image and network processing, cryptography, scientific and high performance embedded computing. However, further improvements of FPGA circuits cannot rely on just lateral device shrinking since CMOS technology is getting already close to its fundaments scaling limits and other opportunities must be explored. One such opportunity is presented by the fact that in contemporary FPGAs, the performance overhead for reconfigurability is very high causing "useful"resources to take only a small fraction of the area of a chip. In this work, PIs focus on hybrid technology FPGAs, in which all configurations bits are implemented in monolithically stacked layers of metallization as resistance switching (i.e., memristive) crosspoint devices integrated on top of a silicon substrate. Preliminary results indicate that even without any optimization and using only conventional CMOS technology, the proposed circuits efficiently hide configuration overhead, and can thus be at least ten times denser (and potentially faster) than CMOS FPGAs with the same design rules and similar power density. To substantiate these claims PIs proposed rigorous interdisciplinary research agenda with three main thrusts: 1) investigation of circuit and architectural innovations, including optimal logic and routing architectures taking into account constraints of state-of-the-art fabrication technology; 2) detailed performance estimation based on physical models of the most promising crosspoint memristive devices; 3) development of design automation tools to map arbitrary circuits onto novel fabrics, including fabric-aware logic synthesis and defect tolerant placement and routing.

现场可编程门阵列（FPGA）成为传统微处理器和专用集成电路的越来越有吸引力的替代品。 事实上，FPGA联合收割机了两者的最佳特性，例如高度定制的数据路径和成本效率，而在过去几十年中，随着互补金属氧化物半导体（CMOS）技术的小型化，FPGA的容量现在接近一百万个可编程逻辑块。 这为FPGA的使用开辟了新的机会，特别是在信号，图像和网络处理，密码学，科学和高性能嵌入式计算中。 然而，FPGA电路的进一步改进不能仅仅依赖于横向器件缩小，因为CMOS技术已经接近其基本的缩放极限，必须探索其他机会。 一个这样的机会是由以下事实呈现的：在当代FPGA中，可重构性的性能开销非常高，导致“有用“资源仅占用芯片面积的一小部分。 在这项工作中，PI重点关注混合技术FPGA，其中所有配置位都在单片堆叠的金属化层中实现为电阻开关（即，忆阻）交叉点器件。 初步结果表明，即使没有任何优化，只使用传统的CMOS技术，所提出的电路有效地隐藏配置开销，因此可以至少10倍的密度（和潜在的速度）比CMOS FPGA具有相同的设计规则和类似的功率密度。 为了证实这些主张，PI提出了严格的跨学科研究议程，主要有三个方面：1）研究电路和架构创新，包括考虑最先进制造技术约束的最佳逻辑和布线架构; 2）基于最有前途的交叉点忆阻器件的物理模型进行详细的性能评估; 3）开发设计自动化工具以将任意电路映射到新颖结构上，包括结构感知逻辑合成和缺陷容限布局和布线。