SHF: Small: Design, Modeling and Automation of Monolithically Stackable Hybrid CMOS/Memristor Programmable Circuits

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Field Programmable Gate Arrays (FPGAs) become increasingly attractive alternatives to conventional microprocessors and application specific integrated circuits. Indeed, FPGAs combine the best properties of both, such as highly customized datapath and cost efficiency, while with miniaturization of complementary metal oxide semiconductor (CMOS) technology during past decades the capacity of FPGAs is now close to a million programmable logic blocks. This opens new opportunities for the use of FPGAs, in particular, in signal, image and network processing, cryptography, scientific and high performance embedded computing. However, further improvements of FPGA circuits cannot rely on just lateral device shrinking since CMOS technology is getting already close to its fundaments scaling limits and other opportunities must be explored. One such opportunity is presented by the fact that in contemporary FPGAs, the performance overhead for reconfigurability is very high causing "useful"resources to take only a small fraction of the area of a chip. In this work, PIs focus on hybrid technology FPGAs, in which all configurations bits are implemented in monolithically stacked layers of metallization as resistance switching (i.e., memristive) crosspoint devices integrated on top of a silicon substrate. Preliminary results indicate that even without any optimization and using only conventional CMOS technology, the proposed circuits efficiently hide configuration overhead, and can thus be at least ten times denser (and potentially faster) than CMOS FPGAs with the same design rules and similar power density. To substantiate these claims PIs proposed rigorous interdisciplinary research agenda with three main thrusts: 1) investigation of circuit and architectural innovations, including optimal logic and routing architectures taking into account constraints of state-of-the-art fabrication technology; 2) detailed performance estimation based on physical models of the most promising crosspoint memristive devices; 3) development of design automation tools to map arbitrary circuits onto novel fabrics, including fabric-aware logic synthesis and defect tolerant placement and routing.